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Accelerating time series motif discovery in the Intel Xeon Phi KNL processor
by
Plata, Oscar
, Villegas, Alejandro
, Gutierrez, Eladio
, Fernandez, Ivan
in
Algorithms
/ Bandwidths
/ Microprocessors
/ Modules
/ Performance enhancement
/ Performance evaluation
/ Time series
2019
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Accelerating time series motif discovery in the Intel Xeon Phi KNL processor
by
Plata, Oscar
, Villegas, Alejandro
, Gutierrez, Eladio
, Fernandez, Ivan
in
Algorithms
/ Bandwidths
/ Microprocessors
/ Modules
/ Performance enhancement
/ Performance evaluation
/ Time series
2019
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Accelerating time series motif discovery in the Intel Xeon Phi KNL processor
Journal Article
Accelerating time series motif discovery in the Intel Xeon Phi KNL processor
2019
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Overview
Time series analysis is an important research topic of great interest in many fields. Recently, the Matrix Profile method, and particularly one of its implementations—the SCRIMP algorithm—has become a state-of-the-art approach in this field. This is a technique that brings the possibility of obtaining exact motifs from a time series, which can be used to infer events, predict outcomes, detect anomalies and more. However, the memory-bound nature of the SCRIMP algorithm limits the execution performance in some processor architectures. In this paper, we analyze the SCRIMP algorithm from the performance viewpoint in the context of the Intel Xeon Phi Knights Landing architecture (KNL), which integrates high-bandwidth memory (HBM) modules, and we combine several techniques aimed at exploiting the potential of this architecture. On the one hand, we exploit the multi-threading and vector capabilities of the architecture. On the other hand, we explore how to allocate data in order to take advantage of the available hybrid memory architecture that conjugates both the high-bandwidth 3D-stacked HBM and the DDR4 memory modules. The experimental evaluation shows a performance improvement up to 190× with respect to the sequential execution and that the use of the HBM memory improves performance in a factor up to 5× with respect to the DDR4 memory.
Publisher
Springer Nature B.V
Subject
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