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The non-polymorphic HLA-E molecule offers opportunities for new universal immunotherapeutic approaches to chronic infectious diseases. Chronic Hepatitis B virus (HBV) infection is driven in part by T cell dysfunction due to elevated levels of the HBV envelope (Env) protein hepatitis B surface antigen (HBsAg). Here we report the characterization of three genotypic variants of an HLA-E-binding HBsAg peptide, Env 371-379, identified through bioinformatic predictions and verified by biochemical and cellular assays. Using a soluble affinity-enhanced T cell receptor (TCR) (a09b08)-anti-CD3 bispecific molecule to probe HLA-E presentation of the Env 371-379 peptides, we demonstrate that only the most stable Env 371-379 variant, L6I, elicits functional responses to a09b08-anti-CD3-redirected polyclonal T cells co-cultured with targets expressing endogenous HBsAg. Furthermore, HLA-E-Env 371-379 L6I-specific CD8 + T cells are detectable in HBV-naïve donors and people with chronic HBV after in vitro priming. In conclusion, we provide evidence for HLA-E-mediated HBV Env peptide presentation, and highlight the effect of viral mutations on the stability and targetability of pHLA-E molecules. Chronic Hepatitis B virus (HBV) is associated with elevated levels of hepatitis B surface antigen (HBsAg). Here the authors characterize the T cell responses to three variants of an HBsAg, Evn371-379, to find only the most stable L6I variant eliciting HBsAg responses, while T cells specific for L6I are detectable in both control and people with chronic HBV.

Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation.

— This article presents the description of a prototype readout electronics for capacitive detectors based on an application-specific integrated circuit (ASIC) designed specifically for the readout and pre-processing of signals from the flat resistive chambers of the SPD (spectrometer with pixel detectors) experiment at the NICA collider under construction at JINR (Joint Institute for Nuclear Research) in Dubna. The eight-channel ASIC is optimized to work with detectors featuring a characteristic impedance of the readout electrodes in the range of 35–110 Ω, with an equivalent input noise charge of no more than 2500 electrons. The ASIC includes adjustments for the threshold by the input charge in the range of 10–450 fC, hysteresis of the threshold characteristic in the range of 0–12%, and signal extension time in the range of 0.5–100 ns. The circuit was optimized to reduce jitter on the front edge (less than 10 ps) and power consumption (less than 25 mW per channel).

An application of the deconvolution method for signal peak detection in read-out ASIC for GEM detectors is described. Instead of usage of the conventional analog or digital peak detector, deconvolution technique to define the signal maximum was studied. In this case the digital data coming from the ADC are processed by a digital filter that deconvolves according to the pre-determined transfer function of the analog channel. Such processing allows to identify the signal peak values and also to provide reasonable pileup rejection. That enables higher rates of the incoming signals and reduces the amount of lost data. Combined with the analog channel employing 10-bit 25 MHz sampling rate ADC and 250 ns time constant 2nd-order shaper, the designed deconvolution block maintains peak detection accuracy within 9 LSBs. Time resolution of peak separation is 4 ADC sampling intervals or 100 ns.

A low power area efficient 5 bit current steering DAC is presented. The proposed DAC is integrated to prototype the readout channel for muon chamber in CBM experiment. DAC was implemented with an area of 0.019 mm2 in the CMOS process using UMS MMRF 180 nm technology. This DAC has ultralow power consumption - 25μW. The measured differential nonlinearity (DNL) is better than 0.25 LSB, integral nonlinearity (INL) is better than 0.2 LSB. In this paper the main steps of design flow, simulation results and measurement results are presented.

The development of an analog read-out channel for time projection chambers (TPC) is presented both in schematic and layout. Structure of the channel consists of a preamplifier, fourth order shaper and differential buffer. The channel operates with positive and negative polarities of input charge. The prototype has the following features: dynamic range of 100 fC for both polarities, 20 mv/fC of sensitivity for differential output, peaking time - 160 ns, ENC - <1000e at 40 pF of source capacitance. The presented channel was designed and verified in the CMOS UMC MMRF 180 nm process. The results of post layout simulation are presented.

A prototype of an analog channel with a digital processing system for reading signals from GEM detectors is presented. Each channel consists of a charge-sensitive amplifier, a shaper, a switch, an amplifier and a 10-bits ADC. The data from the ADC is processed by the digital system based on an interpolator to find signal peaks. The interpolator uses a 6th order Lagrange polynomial. It maintains peak detection accuracy within 1.1 LSB at 25 MHz ADC sampling rate and 270 ns shaper peaking time.

The paper describes the approach to designing built-in monitoring buffers for the purpose of checking the functionality of ASICs as parts of test printed boards. A figure of merit (FOM), based on that analysis is suggested. Features of the FOM, applied to particle physics experiments, are the speed, power consumption, load driving capability and occupied chip area. As an example, illustrating the choice of buffer according to the proposed FOM, there are presented the results of designing a buffer version as part of an ASIC for the CBM MUCH(http://www.fair-center.eu/for-users/experiments/cbm.html).

The data readout system of multichannel data-driven ASIC, requiring high-speed (320 Mb/s) output data serialization is described. Its structure, based on a limited number of FIFO blocks, provides a lossless data transfer. The solution has been realized as a separate test IP block in the prototyped 8 channel ASIC, intended for the muon chamber of CBM experiment at FAIR. The block was developed for the UMC 0.18 μm MMRF CMOS process and prototyped via Europractice. Main parameters of the chip are given.

The development architecture of a multichannel data-driven ASIC is presented. It provides the selection of useful events at an early stage of reading out detector signals. The architecture is based on fast cross-point switches of analog signals, followed by their digitization by a limited set of ADCs and high-speed output data serialization. Such approach reduces the number of subsequent ADCs as well as digital processing channels. That leads to lower power consumption and chip area. The results of a prototype ASIC development, based on this architecture and intended for the CBM experiment at FAIR, are given.