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Background Regorafenib is an oral multi-tyrosine kinase (RTK) inhibitor. It exhibits high selectivity for VEGFR1/2/3, while also inhibiting PDGFRβ, FGFR1, and oncogenic signaling cascades involving c-RAF/RAF1 and BRAF. These pathways are highly expressed in meningiomas, particularly in high-grade meningiomas. Methods The MIRAGE trial (NCT06275919) is a multicenter, open-label, controlled, randomized phase 2 clinical trial evaluating grade 2/3 meningioma patients who have progressed following surgery and radiotherapy. A total of 94 participants are being randomized (1:1) to receive either regorafenib (160 mg orally for 3 weeks on, 1 week off) or local standard-of-care therapies (e.g., bevacizumab, hydroxyurea, somatostatin analogs). Major inclusion criteria include histological confirmation of grade 2 or grade 3 meningioma according to the WHO 2021 classification, radiologically documented progression according to RANO criteria with at least 1 measurable lesion (minimum 10 × 10 mm) on baseline MRI, ineligibility for further surgery and/or radiotherapy, and a WHO performance status of 0–1. The primary endpoint is 6-month progression-free survival (6m-PFS) and secondary endpoints include overall survival (OS), objective response rate (ORR), disease control rate (DCR), safety, and health-related quality of life. Exploratory analysis will also be performed. MIRAGE, initiated in September 2024, is an academic trial promoted by the Istituto Oncologico Veneto, IOV-IRCCS, and will recruit patients across 15 neuro-oncology centers in Italy with an estimated study duration of 18 months. Discussion MIRAGE is a phase 2 trial designed to determine the role of regorafenib in prolonging the PFS of grade 2–3 meningioma patients ineligible for further surgery and/or radiotherapy. Trial registration ClinicalTrials.gov NCT06275919. Registered before start of inclusion, 7 February 2024. EuCT no. 2024–510954-28.

Glioblastoma (GBM) is the most frequent and aggressive malignant primary central nervous system tumor in adults [...].Glioblastoma (GBM) is the most frequent and aggressive malignant primary central nervous system tumor in adults [...].

Glioblastoma (GBM) is the most aggressive malignant primary central nervous system (CNS) tumor and, despite decades of research, it remains a lethal disease with a median overall survival of less than two years [...]

This work is a survey on approximate computing and its impact on fault tolerance, especially for safety-critical applications. It presents a multitude of approximation methodologies, which are typically applied at software, architecture, and circuit level. Those methodologies are discussed and compared on all their possible levels of implementations (some techniques are applied at more than one level). Approximation is also presented as a means to provide fault tolerance and high reliability: Traditional error masking techniques, such as triple modular redundancy, can be approximated and thus have their implementation and execution time costs reduced compared to the state of the art.

Glioblastoma (GBM) is the most common and aggressive primary malignant brain tumor. Standard therapies, including surgical resection, chemoradiation, and tumor treating fields, have not resulted in major improvements in the survival outcomes of patients with GBM. The lack of effective strategies has led to an increasing interest in immunotherapic approaches, considering the success in other solid tumors. However, GBM is a highly immunosuppressive tumor, as documented by the presence of several mechanisms of immune escape, which may represent a reason why immunotherapy clinical trials failed in this kind of tumor. In this review, we examine the current landscape of immunotherapy strategies in GBM, focusing on the challenge of immunoresistance and potential mechanisms to overcome it. We discussed completed and ongoing clinical trials involving immune checkpoint inhibitors, oncolytic viruses, vaccines, and CAR T-cell therapies, to provide insights into the efficacy and outcomes of different immunotherapeutic interventions. We also explore the impact of radiotherapy on the immune system within the GBM microenvironment highlighting the complex interactions between radiation treatment and the immune response. This review examines the current landscape of immunotherapy strategies in glioblastoma, focusing on the challenge of immunoresistance and potential mechanisms to overcome it.

Approximate Computing (AxC) aims at optimizing the hardware resources in terms of area and power consumption at the cost of a reasonable degradation in computation accuracy. Several design exploration approaches and metrics have been proposed so far to identify the approximation targets, but only a few of them exploit information derived from assertion-based verification (ABV). In this paper we propose an ABV methodology to guide the AxC design exploration of RTL descriptions; we consider two main approximation techniques: bit-width and statement reduction. Assertions are automatically mined from the simulation traces of the original design to capture the golden behaviours. Then, we consider the syntactic and semantic aspects of the assertions to rank the approximation targets. The proposed methodology generates a list of statements sorted by their increasing impact on altering the functional correctness of the original design, when selected to be approximated. Through experiments on a case study, we show that the proposed approach represents a promising solution toward the automation of AxC design exploration at RTL.

Approximate Computing (AxC) has emerged as a promising paradigm to enhance performance and energy efficiency by allowing a controlled trade-off between accuracy and resource consumption. It is extensively adopted across various abstraction levels, from software to architecture and circuit levels, employing diverse methodologies. The primary objective of AxC is to reduce energy consumption for executing error-resilient applications, accepting controlled and inherently acceptable output quality degradation. However, harnessing AxC poses several challenges, including identifying segments within a design amenable to approximation and selecting suitable AxC techniques to fulfill accuracy and performance criteria. This survey provides a comprehensive review of recent methodologies proposed for performing Design Space Exploration (DSE) to find the most suitable AxC techniques, focusing on both hardware and software implementations. DSE is a crucial design process where system designs are modeled, evaluated, and optimized for various extra-functional system behaviors such as performance, power consumption, energy efficiency, and accuracy. A systematic literature review was conducted to identify papers that ascribe their DSE algorithms, excluding those relying on exhaustive search methods. This survey aims to detail the state-of-the-art DSE methodologies that efficiently select AxC techniques, offering insights into their applicability across different hardware platforms and use-case domains. For this purpose, papers were categorized based on the type of search algorithm used, with Machine Learning (ML) and Evolutionary Algorithms (EAs) being the predominant approaches. Further categorization is based on the target hardware, including Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), general-purpose Central Processing Units (CPUs), and Graphics Processing Units (GPUs). A notable observation was that most studies targeted image processing applications due to their tolerance for accuracy loss. By providing an overview of techniques and methods outlined in existing literature pertaining to the DSE of AxC designs, this survey elucidates the current trends and challenges in optimizing approximate designs.

This paper presents an overview of test and reliability approaches for approximate computing architectures. We focus on how specific methods for test and reliability can be used to improve the characteristics of approximate computing in terms of power consumption, area, life expectancy and precision. This paper does not address specification and design of approximate hardware/software/algorithms, but provides an in-depth knowledge on how the reliability and test related techniques can be efficiently used to maximize the benefits of approximate computing.

In this paper, we present an analytical methodology to measure the vulnerability of the memory components of a microprocessor-based computing system. It is based on the data and the instruction lifetime and residence. The proposed approach considers only the software-layer of the system, which makes it usable at early design stage when the hardware architecture is not fully defined. Then, to consider the hardware memory hierarchy (i.e., RAM, Caches, Register Files) at software level, we have developed a memory subsystem emulator that can be easily configured to support different features. The methodology can be used to perform a fast, easy and not costly cache-aware Design Space Exploration (DSE) to accurately evaluate the vulnerability of the RAM and the caches. The first set of experiments run on Mibench benchmarks shows that we can perform a fast, easy and not costly DSE to accurately evaluate the effects of the faults in both the RAM and the caches. In addition, we validate the proposed approach on a real industrial test case, which is a Flight Management System for avionic application. The results show that the proposed methodology give precise results compared to a classical fault injection tool, and it scales well with the complexity of the application.

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.