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34 result(s) for "Cao, Chenhong"
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A Low-Power Hardware Architecture for Real-Time CNN Computing
Convolutional neural network (CNN) is widely deployed on edge devices, performing tasks such as objective detection, image recognition and acoustic recognition. However, the limited resources and strict power constraints of edge devices pose a great challenge to applying the computationally intensive CNN models. In addition, for the edge applications with real-time requirements, such as real-time computing (RTC) systems, the computations need to be completed considering the required timing constraint, so it is more difficult to trade off between computational latency and power consumption. In this paper, we propose a low-power CNN accelerator for edge inference of RTC systems, where the computations are operated in a column-wise manner, to realize an immediate computation for the currently available input data. We observe that most computations of some CNN kernels in deep layers can be completed in multiple cycles, while not affecting the overall computational latency. Thus, we present a multi-cycle scheme to conduct the column-wise convolutional operations to reduce the hardware resource and power consumption. We present hardware architecture for the multi-cycle scheme as a domain-specific CNN architecture, which is then implemented in a 65 nm technology. We prove our proposed approach realizes up to 8.45%, 49.41% and 50.64% power reductions for LeNet, AlexNet and VGG16, respectively. The experimental results show that our approach tends to cause a larger power reduction for the CNN models with greater depth, larger kernels and more channels.
QoS-Aware Joint Task Scheduling and Resource Allocation in Vehicular Edge Computing
Vehicular edge computing (VEC) has emerged in the Internet of Vehicles (IoV) as a new paradigm that offloads computation tasks to Road Side Units (RSU), aiming to thereby reduce the processing delay and resource consumption of vehicles. Ideal computation offloading policies for VEC are expected to achieve both low latency and low energy consumption. Although existing works have made great contributions, they rarely consider the coordination of multiple RSUs and the individual Quality of Service (QoS) requirements of different applications, resulting in suboptimal offloading policies. In this paper we present FEVEC, a Fast and Energy-efficient VEC framework, with the objective of realizing an optimal offloading strategy that minimizes both delay and energy consumption. FEVEC coordinates multiple RSUs and considers the application-specific QoS requirements. We formalize the computation offloading problem as a multi-objective optimization problem by jointly optimizing offloading decisions and resource allocation, which is a mixed-integer nonlinear programming (MINLP) problem and NP-hard. We propose MOV, a Multi-Objective computing offloading method for VEC. First, vehicle prejudgment is proposed to meet the requirements of different applications by considering the maximum tolerance delay related to the current vehicle speed. Second, an improved Non-dominated Sorting Genetic Algorithm-II (NSGA-II) is adopted to obtain the Pareto-optimal solutions with low complexity. Finally, the optimal offloading strategy is selected for QoS maximization. Extensive evaluation results based on real and simulated vehicle trajectories verify that the average QoS value of MOV is improved by 20% compared with the state-of-the-art VEC mechanism.
Communication-Traffic-Assisted Mining and Exploitation of Buffer Overflow Vulnerabilities in ADASs
Advanced Driver Assistance Systems (ADASs) are crucial components of intelligent vehicles, equipped with a vast code base. To enhance the security of ADASs, it is essential to mine their vulnerabilities and corresponding exploitation methods. However, mining buffer overflow (BOF) vulnerabilities in ADASs can be challenging since their code and data are not publicly available. In this study, we observed that ADAS devices commonly utilize unencrypted protocols for module communication, providing us with an opportunity to locate input stream and buffer data operations more efficiently. Based on the above observation, we proposed a communication-traffic-assisted ADAS BOF vulnerability mining and exploitation method. Our method includes firmware extraction, a firmware and system analysis, the locating of risk points with communication traffic, validation, and exploitation. To demonstrate the effectiveness of our proposed method, we applied our method to several commercial ADAS devices and successfully mined BOF vulnerabilities. By exploiting these vulnerabilities, we executed the corresponding commands and mapped the attack to the physical world, showing the severity of these vulnerabilities.
Integrated safety and security enhancement of connected automated vehicles using DHR architecture
Safety and security are interrelated and both essential for connected automated vehicles (CAVs). They are usually investigated independently, followed by standards ISO 26262 and ISO/SAE 21434, respectively. However, more functional safety and security features of in-vehicle components make existing safety mechanisms weaken security mechanisms and vice versa. This results in a dilemma that the safety-critical and security-critical in-vehicle components cannot be protected. In this paper, we propose a dynamic heterogeneous redundancy (DHR) architecture to enhance the safety and security of CAVs simultaneously. We first investigate the current status of integrated safety and security analysis and explore the relationship between safety and security. Then, we propose a new taxonomy of in-vehicle components based on safety and security features. Finally, a dynamic heterogeneous redundancy (DHR) architecture is proposed to guarantee integrated functional safety and cyber security of connected vehicles for the first time. A case study on an automated bus shows that DHR architecture can not only detect unknown failures and ensure functional safety but also detect unknown attacks to protect cyber security. Furthermore, we provide an in-depth analysis of quantification for CAVs performance using DHR architecture and identify challenges and future research directions. Overall, integrated safety and security enhancement is an emerging research direction.
TOC: Lightweight Event Tracing Using Online Compression for Networked Embedded Systems
Many trace-based diagnostic techniques have been proposed for abnormal detection and fault diagnosis in networked embedded systems such as wireless sensor networks (WSNs). Event tracing is a nontrivial task for resource-constrained embedded devices. Existing tracing approaches employ compression algorithms to reduce the trace size. However, these approaches either are inapplicable or perform poorly. In this paper, we propose TOC, a novel event tracing technique using online compression. TOC combines periodical pattern mining and efficient token assignment, effectively reducing the trace size with acceptable execution overhead. We implement TOC based on TinyOS 2.1.2 and evaluate its effectiveness by case studies in sensor network applications. Results show that TOC reduces the trace size by 52.2%, compared with LIS—a state-of-the-art event tracing method.
LiveEar: An Efficient and Easy-to-use Liveness Detection System for Voice Assistants
Voice assistants, such as Amazon Alexa, Apple Siri and Tmall Genie, using voice biometrics for the identity authentication, are becoming pervasive in our daily lives. However, voice assistants are vulnerable to reply attack due to the open nature of voice-input channels. An attacker can record the voice commands of victims and replay them to spoof voice assistants. Existing liveness detection approaches are mostly based on machine learning methods, which are expensive and complex. Recently, several approaches are proposed to leverage the human specific voice features or the distinctness of voice played by loudspeaker. However, they require the users and the voice assistant to be in a fixed position and at a very close distance, which is not user-friendly in practice. This paper proposes LiveEar, an efficient and easy-to-use liveness detection system for voice assistant. LiveEar utilizes the differences in phoneme positions between live-human voices and voices replayed through loudspeakers. Specifically, it calculates the time-difference-of-arrival (TDoA) in a sequence of phoneme sounds to the microphone on the voice assistant. Then, an SVM-based classification model is trained with the extracted TDoA features. This paper implements a prototype of LiveEar and evaluates its performance using real-world data. Results show that LiveEar achieves high detection accuracy in various flexible positions, with negligible runtime overhead.
Accelerating Matrix Factorization by Dynamic Pruning for Fast Recommendation
Matrix factorization (MF) is a widely used collaborative filtering (CF) algorithm for recommendation systems (RSs), due to its high prediction accuracy, great flexibility and high efficiency in big data processing. However, with the dramatically increased number of users/items in current RSs, the computational complexity for training a MF model largely increases. Many existing works have accelerated MF, by either putting in additional computational resources or utilizing parallel systems, introducing a large cost. In this paper, we propose algorithmic methods to accelerate MF, without inducing any additional computational resources. In specific, we observe fine-grained structured sparsity in the decomposed feature matrices when considering a certain threshold. The fine-grained structured sparsity causes a large amount of unnecessary operations during both matrix multiplication and latent factor update, increasing the computational time of the MF training process. Based on the observation, we firstly propose to rearrange the feature matrices based on joint sparsity, which potentially makes a latent vector with a smaller index more dense than that with a larger index. The feature matrix rearrangement is given to limit the error caused by the later performed pruning process. We then propose to prune the insignificant latent factors by an early stopping process during both matrix multiplication and latent factor update. The pruning process is dynamically performed according to the sparsity of the latent factors for different users/items, to accelerate the process. The experiments show that our method can achieve 1.2-1.65 speedups, with up to 20.08% error increase, compared with the conventional MF training process. We also prove the proposed methods are applicable considering different hyperparameters including optimizer, optimization strategy and initialization method.
MDHP-Net: Detecting Injection Attacks on In-vehicle Network using Multi-Dimensional Hawkes Process and Temporal Model
The integration of intelligent and connected technologies in modern vehicles, while offering enhanced functionalities through Electronic Control Unit and interfaces like OBD-II and telematics, also exposes the vehicle's in-vehicle network (IVN) to potential cyberattacks. In this paper, we consider a specific type of cyberattack known as the injection attack. As demonstrated by empirical data from real-world cybersecurity adversarial competitions(available at https://mimic2024.xctf.org.cn/race/qwmimic2024 ), these injection attacks have excitation effect over time, gradually manipulating network traffic and disrupting the vehicle's normal functioning, ultimately compromising both its stability and safety. To profile the abnormal behavior of attackers, we propose a novel injection attack detector to extract long-term features of attack behavior. Specifically, we first provide a theoretical analysis of modeling the time-excitation effects of the attack using Multi-Dimensional Hawkes Process (MDHP). A gradient descent solver specifically tailored for MDHP, MDHP-GDS, is developed to accurately estimate optimal MDHP parameters. We then propose an injection attack detector, MDHP-Net, which integrates optimal MDHP parameters with MDHP-LSTM blocks to enhance temporal feature extraction. By introducing MDHP parameters, MDHP-Net captures complex temporal features that standard Long Short-Term Memory (LSTM) cannot, enriching temporal dependencies within our customized structure. Extensive evaluations demonstrate the effectiveness of our proposed detection approach.
Interactions between gut microbiota, host genetics and diet relevant to development of metabolic syndromes in mice
Both genetic variations and diet-disrupted gut microbiota can predispose animals to metabolic syndromes (MS). This study assessed the relative contributions of host genetics and diet in shaping the gut microbiota and modulating MS-relevant phenotypes in mice. Together with its wild-type (Wt) counterpart, the Apoa- I knockout mouse, which has impaired glucose tolerance (IGT) and increased body fat, was fed a high-fat diet (HFD) or normal chow (NC) diet for 25 weeks. DNA fingerprinting and bar-coded pyrosequencing of 16S rRNA genes were used to profile gut microbiota structures and to identify the key population changes relevant to MS development by Partial Least Square Discriminate Analysis. Diet changes explained 57% of the total structural variation in gut microbiota, whereas genetic mutation accounted for no more than 12%. All three groups with IGT had significantly different gut microbiota relative to healthy Wt/NC-fed animals. In all, 65 species-level phylotypes were identified as key members with differential responses to changes in diet, genotype and MS phenotype. Most notably, gut barrier-protecting Bifidobacterium spp. were nearly absent in all animals on HFD, regardless of genotype. Sulphate-reducing, endotoxin-producing bacteria of the family, Desulfovibrionaceae , were enhanced in all animals with IGT, most significantly in the Wt/HFD group, which had the highest calorie intake and the most serious MS phenotypes. Thus, diet has a dominating role in shaping gut microbiota and changes of some key populations may transform the gut microbiota of Wt animals into a pathogen-like entity relevant to development of MS, despite a complete host genome.
Giant enhancement and quick stabilization of capacitance in antiferroelectrics by phase transition engineering
The antiferroelectric-ferroelectric phase transition is a basic principle that holds promise for antiferroelectric ceramics in high capacitance density nonlinear capacitors. So far, the property optimization based on antiferroelectric-ferroelectric transition is solely undertaken by chemical composition tailoring. Alternately, here we propose a phase transition engineering tactic by applying pulsed electric stimulus near the critical electric field, which finally results in ~54.3% enhancement and quick stabilization of capacitance density in Pb 0.97 La 0.02 (Zr 0.35 Sn 0.55 Ti 0.10 )O 3 antiferroelectric ceramics. Ex-situ and in-situ structural characterizations show that electric stimuli can induce the charming successive structural evolution, including domain evolution from multidomain to monodomain state, and modulation period change from 7.49 to 7.73. Structure-property correlation indicates that the antiferroelectric-ferroelectric phase transition engineering mainly stems from the unexpected irreversible recovery of the modulated structures. The present findings would deepen the understanding of the structural phase transition and provoke composition-independent post-treatment property innovation in the incommensurate antiferroelectric materials and devices. The authors utilize the pulsed electric stimulus near the critical electric field to perform the antiferroelectric-ferroelectric phase transition engineering, realizing enhancement and quick stabilization of capacitance in antiferroelectrics.