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Multiplication is a fundamental mathematical operation that finds extensive applications across various disciplines, particularly in computation-intensive and error-resilient applications, such as image processing. As hardware circuits become more complex, there is a growing demand for approximation circuit methods. Implementation of approximate multipliers has the potential to yield substantial reductions in hardware costs while maintaining acceptable performance levels. Most current designs for approximate multipliers are optimized for ASIC-based circuits, which may not produce similar performance improvements when adapted for FPGA-based circuits. Additionally, many of these existing multiplier designs are limited to unsigned numbers. This paper proposes a novel approach for designing signed approximate multipliers tailored specifically for FPGAs. Two efficient architectures are introduced that efficiently utilize key FPGA components, such as LUTs and Carry4 primitives, by designing the optimal LUT-Carry4 netlists. A Pareto-based analysis is also performed to balance trade-offs and achieve a low mean error distance (MED). Simulation results confirm that the proposed architectures offer superior performance compared to existing signed approximate multipliers, delivering improved power efficiency, reduced resource usage, shorter critical path delay (CPD), and enhanced computational accuracy. The practical applicability of these approximate multipliers is further validated through their use in image processing applications.

Two-dimensional (2D) convolution is a low-level processing algorithm used in numerous image processing applications. The significant computing overhead associated with the algorithm often limits the kernel size used in the operation. Kernel separability is one of the techniques used to reduce the computational complexity of 2D convolution. This paper presents two novel resource-efficient 2D convolution architectures based on kernel separability and folding transformation: folded separable convolution architecture and register minimized folded separable convolution architecture. The precedence constraints between the different functional units in the convolution architecture necessitate some pre-processing before the folding transformation so that the top-level functionality is not compromised. This mainly involves retiming the inherent convolution architecture to ensure a complete timing closure of the folded architecture. While retiming enables the architecture to be clocked at higher frequencies, it often has an associated register overhead. To avoid this, the register minimization technique is used novelly, such that the number of registers is reduced to a minimum without increasing the complexity of the architecture. In addition, proposed architectures do not use any line buffer to store interim results, considerably decreasing the on-chip resources and power consumption. The proposed architectures are implemented on different FPGA devices such as Artix-7, Virtex-7, Virtex-4, CycloneV, and ZynQ-7000. Compared to existing architectures, the proposed architectures show a significant reduction in power dissipation, memory bandwidth, hardware utilization, and timing at the expense of a slight decrease in throughput.