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Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures.

The controller area network (CAN) is one of the most popular intra-vehicular communication protocols in the automotive industry. Due to its simplicity and broadcasting technique, the CAN bus protocols have some vulnerabilities. In the last couple of years, security attacks on vehicles have been increasing significantly. These acute attacks remain undetected by the conventional CAN protocol. In this paper, we propose a method that can prevent many kinds of CAN bus monitoring attacks without any change in the underlying CAN protocol. The experimental results demonstrate that our proposed methodology is useful for preventing as well as defending against attacks on the CAN bus. In the worst-case scenario, the proposed algorithm requires 0.41 s to detect an attack and prevent the attack by dynamically updating the message arbitration ID of a system comprising twelve types of message IDs.

The DARPA POSH program echoes with the research community and identifies that engineering productivity has fallen behind Moore’s law, resulting in the prohibitive increase in IC design cost at leading technology nodes. The primary reason is that it requires many computing resources, expensive tools, and even many days to complete a design implementation. However, at the end of this process, some designs could not meet the design constraints and become unroutable, creating a vicious circuit design cycle. As a result, designers have to re-run the whole process after design modification. This research applied a machine learning approach to automatically identify design constraints and design rule checking (DRC) violation issues and help the designer identify design constraints with optimal DRCs before the long detailed routing process through iterative greedy search. The proposed algorithm achieved up to 99.99% design constraint prediction accuracy and reduced 98.4% DRC violations with only a 6.9% area penalty.

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C2-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

Generative artificial intelligence (G-AI) has moved from proof-of-concept demonstrations to practical tools that augment radiology, dermatology, genetics, drug discovery, and electronic-health-record analysis. This mini-review synthesizes fifteen studies published between 2020 and 2025 that collectively illustrate three dominant trends: data augmentation for imbalanced or privacy-restricted datasets, automation of expert-intensive tasks such as radiology reporting, and generation of new biomedical knowledge ranging from molecular scaffolds to fairness insights. Image-centric work still dominates, with GANs, diffusion models, and Vision-Language Models expanding limited datasets and accelerating diagnosis. Yet narrative (EHR) and molecular design domains are rapidly catching up. Despite demonstrated accuracy gains, recurring challenges persist: synthetic samples may overlook rare pathologies, large multimodal systems can hallucinate clinical facts, and demographic biases can be amplified. Robust validation, interpretability techniques, and governance frameworks therefore, remain essential before G-AI can be safely embedded in routine care.

The controller area network (CAN) remains the de facto standard for intra-vehicular communication. CAN enables reliable communication between various microcontrollers and vehicle devices without a central computer, which is essential for sustainable transportation systems. However, it poses some serious security threats due to the nature of communication. According to caranddriver.com, there were at least 150 automotive cybersecurity incidents in 2019, a 94% year-over-year increase since 2016, according to a report from Upstream Security. To safeguard vehicles from such attacks, securing CAN communication, which is the most relied-on in-vehicle network (IVN), should be configured with modifications. In this paper, we developed a configurable CAN communication protocol to secure CAN with a hardware prototype for rapidly prototyping attacks, intrusion detection systems, and response systems. We used a field programmable gate array (FPGA) to prototype CAN to improve reconfigurability. This project focuses on attack detection and response in the case of bus-off attacks. This paper introduces two main modules: the multiple generic errors module with the introduction of the error state machine (MGEESM) module and the bus-off attack detection (BOAD) module for a frame size of 111 bits (BOAD111), based on the CAN protocol presenting the introduction of form error, CRC error, and bit error. Our results show that, in the scenario with the transmit error counter (TEC) value 127 for switching between the error-passive state and bus-off state, the detection times for form error, CRC error, and bit error introduced in the MGEESM module are 3.610 ms, 3.550 ms, and 3.280 ms, respectively, with the introduction of error in consecutive frames. The detection time for BOAD111 module in the same scenario is 3.247 ms.

Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor–capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1–5 GHz frequency, compared to conventional primary–secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power savings and 6.5× reduced skew while using the proposed pulsed resonant flip-flop and saves 64% power and 12.7× reduced skew while using the proposed resonant true single-phase clock (TSPC) flip-flop.

Speech Emotion Recognition (SER), the extraction of emotional features with the appropriate classification from speech signals, has recently received attention for its emerging social applications. Emotional intensity (e.g., Normal, Strong) for a particular emotional expression (e.g., Sad, Angry) has a crucial influence on social activities. A person with intense sadness or anger may fall into severe disruptive action, eventually triggering a suicidal or devastating act. However, existing Deep Learning (DL)-based SER models only consider the categorization of emotion, ignoring the respective emotional intensity, despite its utmost importance. In this study, a novel scheme for Recognition of Emotion with Intensity from Speech (REIS) is developed using the DL model by integrating three speech signal transformation methods, namely Mel-frequency Cepstral Coefficient (MFCC), Short-time Fourier Transform (STFT), and Chroma STFT. The integrated 3D form of transformed features from three individual methods is fed into the DL model. Moreover, under the proposed REIS, both the single and cascaded frameworks with DL models are investigated. A DL model consists of a 3D Convolutional Neural Network (CNN), Time Distribution Flatten (TDF) layer, and Bidirectional Long Short-term Memory (Bi-LSTM) network. The 3D CNN block extracts convolved features from 3D transformed speech features. The convolved features were flattened through the TDF layer and fed into Bi-LSTM to classify emotion with intensity in a single DL framework. The 3D transformed feature is first classified into emotion categories in the cascaded DL framework using a DL model. Then, using a different DL model, the intensity level of the identified categories is determined. The proposed REIS has been evaluated on the Ryerson Audio-Visual Database of Emotional Speech and Song (RAVDESS) benchmark dataset, and the cascaded DL framework is found to be better than the single DL framework. The proposed REIS method has shown remarkable recognition accuracy, outperforming related existing methods.

Over the past decade, power associated with the Clock Distribution Network (CDN) has played an increasingly important role in the global integrated circuit industry. Since Complementary Metal Oxide Semiconductor (CMOS) technology continues to shrink, new physical phenomena are added to device/transistor behaviour. However, less attention has been given to add more features to the interconnect materials. In order to reduce the power associated with interconnect, researchers introduced some efficient low power techniques like low-swing clock signaling, clock gating, and resonant energy recovery clocking. Another very attractive signaling scheme, namely Current-Mode (CM) signaling, can save significant power while maintaining high frequency operation. However, a true CM clocking methodology for local and global CDNs has not been explored. I propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While CM signaling has been used in one-to-one signals, this is the first usage in a one-to-many CDN. To accomplish this, I create a new high-performance current-mode pulsed flipflop with enable (CMPFFE) using a representative 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage-mode (VM) clocks. In addition, I propose the first CM clock synthesis (CMCS) methodology to reduce overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. I validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks. This methodology saves 39–84% average power with similar skew on the benchmarks using 45nm CMOS technology simulation of clock frequencies range from 1–3GHz. In addition, the CMCS methodology takes 2.4–9.1× less running time and consumes 20–26% less transistor area compared to synthesized, buffered VM clock distributions.

BackgroundSouth Asian ancestry populations are underrepresented in genomic studies and therapeutics trials. British South Asians suffer from multi-morbidity leading to polypharmacy. Our objective was to elucidate British South Asian ancestry community perspectives on pharmacogenomic implementation and sharing pharmacogenomic clinical data for research.MethodsFour focus groups were conducted (9–12 participants in each). Two groups were mixed gender, while one group was male only and one was female only. Simultaneous interpretation was available to participants in Urdu and Bengali. Focus groups were recorded and abridged transcription and thematic analysis were undertaken.ResultsThere were 42 participants, 64% female. 26% were born in the UK or Europe. 52% were born in Bangladesh and 17% in Pakistan. 36% reported university level education.Implementation of pharmacogenomics was perceived to be beneficial to individuals but pose a risk of overburdening resource limited systems. Pharmacogenomic research was perceived to be beneficial to the community, with concerns about data privacy and misuse. Data sharing was desirable if the researchers did not have a financial stake, and benefits would be shared.Trust was the key condition for the acceptability of both clinical implementation and research. Trust was linked with medication compliance. Education, outreach, and communication facilitate trust.Conclusions (Significance and Impact of the Study)Pharmacogenomics implementation with appropriate education and communication has the potential to enhance trust and contribute to increased medication compliance. Trust drives data sharing, which would enable enhanced representation in research. Representation in scientific evidence base could cyclically enhance trust and compliance.