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The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

The design of a starter for a low-voltage, micro-power boost DC–DC converter intended for powering CMOS image sensors is presented. A unique feature of the starter is extremely low current, below 1 nA, supplying its control circuit. Therefore, a high-voltage (1.3 V) configuration of series-connected photovoltaic diodes available in a standard CMOS process or a small external LED working in photovoltaic mode can be used as an auxiliary supply for the control circuit. With this auxiliary supply, the starter can generate a starting voltage from 1 to 2.7 V using 50–200 mV supply voltage. The starter was verified by simulations and measurements of a prototype chip fabricated in a standard 180-nm CMOS technology. The results of simulations and tests showed correct operation of the starter in the temperature from 0 to 50 °C and under process parameters variation.

This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2–3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18- μ m CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.

A novel Gm-C structure of a second-order continuous-time filter is proposed that allows for the independent control of the filter’s natural frequency (ω0) and quality factor (Q). The structure consists of two capacitors and four transconductors. Two transconductors together with the capacitors form a lossless second-order circuit with tunable ω0. The other two transconductors form a variable gain amplifier (VGA) which realizes an adjustable loss and thereby adjustable Q. The proposed solution can be used to implement low-voltage and low-power tunable front-end filter banks for fully integrated CMOS cochlear implants and edge intelligence accelerators. An example filter bank powered by 0.5 V and consuming 40 nW of power per single filter is designed and simulated using a 180 nm CMOS process. Circuitries for the adaptive control of transistor bias at a reduced supply voltage are proposed. The ω0 and Q control circuitries are also proposed: a delay-locked loop (DLL)-based system for fine ω0 tuning and a binary-weighted current mirror for Q adjustment. The proposed solution allows for the independent regulation of ω0 and Q within the ranges of 0.25–8 kHz and 1–14, respectively, with a relative tolerance of up to 5% across a filter bank.

A novel implementation of an analogue low-power, second-order, low-pass filter with tunable quality factor (Q) is presented and discussed. The filter feature is a relatively simple, buffer-based, circuit network consisting of eleven transistors operating in a subthreshold region. Q tuning is accomplished by injecting direct current into a network node, which changes the output resistance of the transistors and, as a result, modifies the filter network’s loss, and thus its Q. Q tuning is independent of a filter cut-off frequency (ω0). The filter, with a nominal ω0 of 1 kHz, was fabricated using a 0.18 µm CMOS technology, and features a Q range of 2–11, power consumption of up to 52 nW, and a 59 dB dynamic range when using a 0.5 V supply. The ω0 can be tuned from 0.5 to 2.5 kHz using a traditional method by changing the transistor transconductances, but this process partially affects the quality factor.

A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

An acoustic second-order low-pass filter is proposed for filter banks emulating the operation of a human cochlea. By using a special filter structure and an innovative quality (Q)-factor tuning technique, an independent change of the cutoff frequency (ω0) and the Q-factor with unchanged gain at low frequencies is achieved in this filter. The techniques applied result in a simple filter design with low Q-factor sensitivity to component mismatch. These filter features greatly simplify the implementation of the electronic cochlea in CMOS technologies. An exemplary filter bank designed and simulated in an X-FAB 180 nm CMOS process is presented, which consumes 1.25–34.75 nW of power per individual filter when supplied with 0.5 V. The 11-channel filter bank covers a 20–20 kHz band, while the Q-factor of each channel can be tuned from 2 to 40. The simulation-predicted sensitivities of Q and ω0 to process/voltage/temperature (PVT) variations are less than 1%. The input-referred noise is no greater than 22 µVRMS, and the dynamic range is at least 68 dB for all filters in the bank.

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.