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Developing a low-cost wireless energy meter with power quality measurements for smart grid applications represents a significant advance in efficient and accurate electric energy monitoring. In increasingly complex and interconnected electric systems, this device will be essential for a wide range of applications, such as smart grids, by introducing a real-time energy monitoring system. In light of this, smart meters can offer greater opportunities for sustainable and efficient energy use and improve the utilization of energy sources, especially those that are nonrenewable. According to the 2020 International Energy Agency (IEA) report, nonrenewable energy sources represent 65% of the global supply chain. The smart meter developed in this work is based on the ESP32 microcontroller and easily accessible components since it includes a user-friendly development platform that offers a cost-effective solution while ensuring reliable performance. The main objective of developing the smart meters was to enhance the software and simplify the hardware. Unlike traditional meters that calculate electrical parameters by means of complex circuits in hardware, this project performed the calculations directly on the microcontroller. This procedure reduced the complexity of the hardware by simplifying the meter design. Owing to the high-performance processing capability of the microcontroller, efficient and accurate calculations of electrical parameters could be achieved without the need for additional circuits. This software-driven approach with simplified hardware led to benefits, such as reduced production costs, lower energy consumption, and a meter with improved accuracy, as well as updates on flexibility. Furthermore, the integrated wireless connectivity in the microcontroller enables the collected data to be transmitted to remote monitoring systems for later analysis. The innovative feature of this smart meter lies in the fact that it has readily available components, along with the ESP32 chip, which results in a low-cost smart meter with performance that is comparable to other meters available on the market. Moreover, it is has the capacity to incorporate IoT and artificial intelligence applications. The developed smart meter is cost effective and energy efficient, and offers benefits with regard to flexibility, and thus represents an innovative, efficient, and versatile solution for smart grid applications.

This study investigates the implementation of artificial intelligence (AI) algorithms on resource-constrained edge devices, such as ESP32 and Raspberry Pi, within the context of smart grid (SG) applications. Specifically, it proposes a smart-meter-based system capable of classifying and detecting the Internet of Things (IoT) electronic devices at the extreme edge. The smart meter developed in this work acquires real-time voltage and current signals from connected devices, which are used to train and deploy lightweight machine learning models—Multi-Layer Perceptron (MLP) and K-Nearest Neighbor (KNN)—directly on edge hardware. The proposed system is integrated into the Artificial Intelligence in the Internet of Things for Smart Grids IAIoSGT architecture, which supports edge–cloud processing and real-time decision-making. A literature review highlights the key gaps in the existing approaches, particularly the lack of embedded intelligence for load identification at the edge. The experimental results emphasize the importance of data preprocessing—especially normalization—in optimizing model performance, revealing distinct behavior between MLP and KNN models depending on the platform. The findings confirm the feasibility of performing accurate low-latency classification directly on smart meters, reinforcing the potential of scalable AI-powered energy monitoring systems in SG.

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

Task mapping and routing are crucial steps in the Networks on Chip (NoC) based Multiprocessor System on Chip (MPSoC) design. While the mapping must ensure an optimized arrangement of the applications’ tasks on the system cores, the routing must ensure the tasks’ communication with the minimum possible delay. We observe that these two problems are highly dependent since finding a routing solution requires first finding a mapping solution. Based on that, this paper analyzes the mapping and routing problems in NoC-based MPSoC and defines a joint version as the Mapping and Routing Problem (MRP). We propose a mathematical model that generates mapping and routing solutions based on a specific bandwidth of NoC links. We also propose three evolutionary metaheuristic algorithms to find optimized solutions to the MRP: Genetic (GA), Memetic (MA), and Transgenetic Algorithms (TA). Experimental results evaluating communication latency demonstrate that the proposed algorithms suit well for the tackled problem, but the TA stands out among all the compared solutions. Overall, TA achieved up to 8% and 19% better performance than the compared algorithms in Global Average Delay and Maximum Delay. Also, it outperformed the other strategies in 55.76% and 51.58% of all the performed simulations in both respective metrics.

Real-time embedded systems need software and hardware to be time-predictable to guarantee the correct behavior of the system. Precision Timed Machines are architectures designed for timing predictability and repeatability. They help to improve design time and the efficiency of real-time embedded systems by allowing to separately verify the timing properties of modules. This paper presents a Simultaneous Multithreading Precision Timed Machine named Hivek-RT that can execute hard real-time and conventional threads in parallel. It employs a repeatable thread-interleaved pipeline with an exposed memory hierarchy composed of scratchpads, caches, and a predictable SDRAM memory controller. The proposed architecture is well suited for real-time embedded systems as experimentation results show that the proposed architecture has improved throughput, presents low memory footprint and achieve a memory bandwidth of 90% of the theoretical value while providing deterministic time access to the memory hierarchy. This paper is an extended version of the paper presented on the 8th Brazilian Symposium on Computing Systems Engineering.