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We propose an efficient hand gesture recognition (HGR) algorithm, which can cope with time-dependent data from an inertial measurement unit (IMU) sensor and support real-time learning for various human-machine interface (HMI) applications. Although the data extracted from IMU sensors are time-dependent, most existing HGR algorithms do not consider this characteristic, which results in the degradation of recognition performance. Because the dynamic time warping (DTW) technique considers the time-dependent characteristic of IMU sensor data, the recognition performance of DTW-based algorithms is better than that of others. However, the DTW technique requires a very complex learning algorithm, which makes it difficult to support real-time learning. To solve this issue, the proposed HGR algorithm is based on a restricted column energy (RCE) neural network, which has a very simple learning scheme in which neurons are activated when necessary. By replacing the metric calculation of the RCE neural network with DTW distance, the proposed algorithm exhibits superior recognition performance for time-dependent sensor data while supporting real-time learning. Our verification results on a field-programmable gate array (FPGA)-based test platform show that the proposed HGR algorithm can achieve a recognition accuracy of 98.6% and supports real-time learning and recognition at an operating frequency of 150 MHz.

This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

Hand gesture recognition, which is one of the fields of human–computer interaction (HCI) research, extracts the user’s pattern using sensors. Radio detection and ranging (RADAR) sensors are robust under severe environments and convenient to use for hand gestures. The existing studies mostly adopted continuous-wave (CW) radar, which only shows a good performance at a fixed distance, which is due to its limitation of not seeing the distance. This paper proposes a hand gesture recognition system that utilizes frequency-shift keying (FSK) radar, allowing for a recognition method that can work at the various distances between a radar sensor and a user. The proposed system adopts a convolutional neural network (CNN) model for the recognition. From the experimental results, the proposed recognition system covers the range from 30 cm to 180 cm and shows an accuracy of 93.67% over the entire range.

In this paper, a method to detect frames was described that can be used as hand gesture data when configuring a real-time hand gesture recognition system using continuous wave (CW) radar. Detecting valid frames raises accuracy which recognizes gestures. Therefore, it is essential to detect valid frames in the real-time hand gesture recognition system using CW radar. The conventional research on hand gesture recognition systems has not been conducted on detecting valid frames. We took the R-wave on electrocardiogram (ECG) detection as the conventional method. The detection probability of the conventional method was 85.04%. It has a low accuracy to use the hand gesture recognition system. The proposal consists of 2-stages to improve accuracy. We measured the performance of the detection method of hand gestures provided by the detection probability and the recognition probability. By comparing the performance of each detection method, we proposed an optimal detection method. The proposal detects valid frames with an accuracy of 96.88%, 11.84% higher than the accuracy of the conventional method. Also, the recognition probability of the proposal method was 94.21%, which was 3.71% lower than the ideal method.

This paper proposes a high-speed continuous wavelet transform (CWT) processor to analyze vital signals extracted from a frequency-modulated continuous wave (FMCW) radar sensor. The proposed CWT processor consists of a fast Fourier transform (FFT) module, complex multiplier module, and inverse FFT (IFFT) module. For high-throughput processing, the FFT and IFFT modules are designed with the pipeline FFT architecture of radix-2 single-path delay feedback (R2SDF) and mixed-radix multipath delay commutator (MRMDC) architecture, respectively. In addition, the IFFT module and the complex multiplier module perform a four-channel operation to reduce the processing time from repeated operations. Simultaneously, the MRMDC IFFT module minimizes the circuit area by reducing the number of non-trivial multipliers by using a mixed-radix algorithm. In addition, the proposed CWT processor can support variable lengths of 8, 16, 32, 64, 128, 256, 512, and 1024 to analyze various vital signals. The proposed CWT processor was implemented in a field-programmable gate array (FPGA) device and verified through the measurement of heartbeat and respiration from an FMCW radar sensor. Experimental results showed that the proposed CWT processor can reduce the processing time by 48.4-fold and 40.7-fold compared to MATLAB software with Intel i7 CPU. Moreover, it can be confirmed that the proposed CWT processor can reduce the processing time by 73.3% compared to previous FPGA-based implementations.

As various unmanned autonomous driving technologies such as autonomous vehicles and autonomous driving drones are being developed, research on FMCW radar, a sensor related to these technologies, is actively being conducted. The range resolution, which is a parameter for accurately detecting an object in the FMCW radar system, depends on the modulation bandwidth. Expensive radars have a large modulation bandwidth, use the band above 77 GHz, and are mainly used as in-vehicle radar sensors. However, these high-performance radars have the disadvantage of being expensive and burdensome for use in areas that require precise sensors, such as indoor environment motion detection and autonomous drones. In this paper, the range resolution is improved beyond the limited modulation bandwidth by extending the beat frequency signal in the time domain through the proposed Adaptive Mirror Padding and Phase Correction Padding. The proposed algorithm has similar performance in the existing Zero Padding, Mirror Padding, and Range RMSE, but improved results were confirmed through the ρs indicating the size of the side lobe compared to the main lobe and the accurate detection rate of the OS CFAR. In the case of ρs, it was confirmed that with single targets, Adaptive Mirror Padding was improved by about 3 times and Phase Correct Padding was improved by about 6 times compared to the existing algorithm. The results of the OS CFAR were divided into single targets and multiple targets to confirm the performance. In single targets, Adaptive Mirror Padding improved by about 10% and Phase Correct Padding by about 20% compared to the existing algorithm. In multiple targets, Phase Correct Padding improved by about 20% compared to the existing algorithm. The proposed algorithm was verified through the MATLAB Tool and the actual FMCW radar. As the results were similar in the two experimental environments, it was verified that the algorithm works in real radar as well.

This paper addresses the challenge of enhancing range precision in radar sensors through supervised learning. However, when the range precision surpasses the range resolution, it leads to a rapid increase in the number of labels, resulting in elevated learning costs. The removal of background noise in indoor environments is also crucial. In response, this study proposes a methodology aiming to increase range precision while mitigating the issue of a growing number of labels in supervised learning. Neural networks learned for a specific section are reused to minimize learning costs and maximize computational efficiency. Formulas and experiments confirmed that identical fractional multiple patterns in the frequency domain can be applied to analyze patterns in other FFT bin positions (representing different target positions). In conclusion, the results suggest that neural networks trained with the same data can be repurposed, enabling efficient hardware implementation.

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

As the autonomous driving technology develops, research on related sensors is also being actively conducted. One system that is widely used today uses a light source with a wavelength in the 905 nm band for the pulse Light Detection And Ranging (LiDAR) system. This has the disadvantages of being harmful to the human eye and in making digital signal processing difficult at high sampling rates. The Frequency Modulated Continuous Wave (FMCW) LiDAR system has been proposed as an alternative. However, the FMCW LiDAR is formed with a high beat frequency by a method different from that of the FMCW Radar, which causes a hardware burden on the FFT (Fast Fourier Transform) module for interpreting the beat frequency information. In this paper, the FFT module that may occur in the FMCW LiDAR using Digital Down Convert (DDC) technology is extracted at 256 points, which is 25 times smaller than the existing 8192 points, and the beat frequency is 0 to 50 m at 3 cm intervals. As a result of generating and restoring the distance, the performance of 0.03 m Root Mean Square Error (RMSE) compared to the conventional one was confirmed. In this process, the hardware module was directly mounted and verified on the FPGA. In the case of the Simple Threshold-Constant False Alarm Rate (ST-CFAR) provided, the RMSE was measured by generating beat frequencies from 0 to 50 m at 1 cm intervals, and as a result, the result of 0.019 m was confirmed at 0.03 m in the past.

Keyword spotting (KWS) systems are used for human–machine communications in various applications. In many cases, KWS involves a combination of wake-up-word (WUW) recognition for device activation and voice command classification tasks. These tasks present a challenge for embedded systems due to the complexity of deep learning algorithms and the need for optimized networks for each application. In this paper, we propose a depthwise separable binarized/ternarized neural network (DS-BTNN) hardware accelerator capable of performing both WUW recognition and command classification on a single device. The design achieves significant area efficiency by redundantly utilizing bitwise operators in the computation of the binarized neural network (BNN) and ternary neural network (TNN). In a complementary metal-oxide semiconductor (CMOS) 40 nm process environment, the DS-BTNN accelerator demonstrated significant efficiency. Compared with a design approach where BNN and TNN were independently developed and subsequently integrated as two separate modules into the system, our method achieved a 49.3% area reduction while yielding an area of 0.558 mm2. The designed KWS system, which was implemented on a Xilinx UltraScale+ ZCU104 field-programmable gate array (FPGA) board, receives real-time data from the microphone, preprocesses them into a mel spectrogram, and uses this as input to the classifier. Depending on the order, the network operates as a BNN or a TNN for WUW recognition and command classification, respectively. Operating at 170 MHz, our system achieved 97.1% accuracy in BNN-based WUW recognition and 90.5% in TNN-based command classification.