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High frame rate three-dimensional (3D) ultrasound imaging would offer excellent possibilities for the accurate assessment of carotid artery diseases. This calls for a matrix transducer with a large aperture and a vast number of elements. Such a matrix transducer should be interfaced with an application-specific integrated circuit (ASIC) for channel reduction. However, the fabrication of such a transducer integrated with one very large ASIC is very challenging and expensive. In this study, we develop a prototype matrix transducer mounted on top of multiple identical ASICs in a tiled configuration. The matrix was designed to have 7680 piezoelectric elements with a pitch of 300 μm × 150 μm integrated with an array of 8 × 1 tiled ASICs. The performance of the prototype is characterized by a series of measurements. The transducer exhibits a uniform behavior with the majority of the elements working within the −6 dB sensitivity range. In transmit, the individual elements show a center frequency of 7.5 MHz, a −6 dB bandwidth of 45%, and a transmit efficiency of 30 Pa/V at 200 mm. In receive, the dynamic range is 81 dB, and the minimum detectable pressure is 60 Pa per element. To demonstrate the imaging capabilities, we acquired 3D images using a commercial wire phantom.

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.