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This paper proposes a physics-based 2-D analytical model for a dual- material gate stack engineered junctionless accumulation-mode cylindrical surrounding gate (DMGSE-JAM-CSG) MOSFET. Analytical modeling is performed using 2-D Poisson’s equation in cylindrical co-ordinate system based upon parabolic potential approximation. This analysis derives the expressions for center potential, electric field, subthreshold drain current, transconductance, output conductance and switching speed. It is seen that this device possesses enhanced drain current, higher transconductance and lower output conductance. The gate-induced drain leakage current for this device has also been investigated. The subthreshold slope of this device is approximately 71 mV/ decade and I on /I off ratio is also high, which leads to its usage for low power and high speed switching applications. The electrical characteristics and short channel effects of this device are also examined for different gate stack materials. It is observed that the device characteristics improve when permittivity of the gate stack is increased. Further, the results acquired using analytical modeling is mapped with the simulated data results to affirm and validate the device model structure. The simulation is implemented using ATLAS-3D device simulator.

The effective control and management of traffic at intersections is a challenging issue in the transportation system. Various traffic signal management systems have been developed to improve the real-time traffic flow at junctions, but none of them have resulted in a smooth and continuous traffic flow for dealing with congestion at road intersections. Notwithstanding, the procedure of synchronizing traffic signals at nearby intersections is complicated due to numerous borders. In traditional systems, the direction of movement of vehicles, the variation in automobile traffic over time, accidents, the passing of emergency vehicles, and pedestrian crossings are not considered. Therefore, synchronizing the signals over the specific route cannot be addressed. This article explores the key role of real-time traffic signal control (TSC) technology in managing congestion at road junctions within smart cities. In addition, this article provides an insightful discussion on several traffic light synchronization research papers to highlight the practicability of networking of traffic signals of an area. It examines the benefits of synchronizing the traffic signals on various busy routes for the smooth flow of traffic at intersections.

This paper presents a method for capacitance scaling of Fractional Capacitor (FC) which is implemented using Current Feedback Operational Amplifiers (CFOA) based Capacitance Multipliers (C Multipliers). The circuit facilitates the change in FC value without changing component values in R-C network used for FC modelling or fabricating a new FC. The performance of the proposed circuit is examined for non ideal effects of CFOA. Effective impedance of scaled FC is examined through MATLAB simulations. The functionality of the realized scalers is verified using SPICE simulations where the FC is modelled using domino RC ladder network. Simulation results for impedance magnitude and phase responses are presented for various scaling factors and are compared with theoretical counterparts. The circuit application of proposed FC scaler is demonstrated through implementation of fractional order lossy and lossless integrators; and may be extended to fractional order filters, oscillators, controllers etc.

With the growing demands of portable devices, it is necessary to pay attention to low-power digital integrated designs. This paper proposes a low-power MOS Current Mode Logic (MCML) design, termed as Hybrid Dynamic Current Mode Logic with modified current source (H-MDyCML). In H-MDyCML circuits, the functions are realized using complementary pass transistor logic which helps to overcome the problem of stacking of transistors in multiple levels. The dynamic current source has also been modified from an NMOS transistor to a PMOS transistor-driven current source which leads to the elimination of the use of CMOS inverter. H-MDyCML circuits are compared with other existing designing styles: Dynamic CML (DyCML), Hybrid DyCML (H-DyCML), and DyCML with modified current source (Dy-CML-NP). The proposed design (H-MDyCML) shows an overall improvement (in terms of Power Delay Product (PDP)) up to 94.77% compared to DyCML, 52.17% compared to Dy-CML-NP, and 91.40% compared to H-DyCML, for single stage circuits.

There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.

This paper presents Signal Flow Graph (SFG) approach-based realization of Single Input Multiple Output (SIMO) filter topologies. A differentiator is placed as basic building block. A total of sixteen variants are derived from the proposed differentiator-based SFG. The Operational Trans-Resistance Amplifier (OTRA), an active block having low parasitics at input terminals, is used to validate the proposed methodology. All the derived filter structures use three OTRAs, six resistors and two capacitors. The filter performance parameters can be adjusted independently. The functional verification of the proposed method is done via SPICE simulations using 0.18 μm CMOS technology parameters from MOSIS.

This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

In this paper, two circuits, namely Footer Voltage Controlled Dual Keeper domino logic (FVCDK) and Footer Voltage Controlled Dual Keeper with Static Switching domino logic (FVCDK-SS) are presented, in order to achieve high speed, low power consumption and robustness. The dual keeper arrangement helps in reducing the loop gain of the feedback circuitry, which leads to lower delay variability. The keeper circuitry is controlled using the footer voltage to reduce the contention current in the initial evaluation phase, and thus providing enhanced speed. In FVCDK-SS domino logic, unwanted transients at the output are reduced by incorporating pseudo-dynamic buffer in the proposed FVCDK domino logic. This further reduces the dynamic power consumption. The results of the logic presented here are validated by comparing them to a wide range of existing domino logic circuits for a~variety of performance metrics such as delay, power, power-delay product and unity noise gain. To effectively gauge the wide fan-in capabilities of the proposed logic, results are shown for the various fan-in OR gate. The simulations of the circuits are carried out using industry standard full-suite Cadence tools using 45~nm technology library.

This paper proposes methods to generate various types of Linear Voltage Transfer Curves (VTC) using Operational Trans-Resistance Amplifier (OTRA) as the active block. It further goes on to propose methods to multiplex various individual Linear VTCs to obtain any form of Piece-Wise Linear Voltage Transfer Curves (PWL), which find many applications in the world of circuitry. One particular application has been highlighted, i.e. generation of High-Frequency Sinusoids. Simulations of the Circuits proposed via Cadence Virtuoso, using TowerJazz’s 180 nm Technology Node have been reported, which satisfy the aim behind its development.