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FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment employing AI techniques. Integrated between the readout of the Ring Imaging Cherenkov detector (RICH) and the low-level trigger processor (L0TP+), FPGA-RICH implements a fast pipeline to process in real-time the RICH raw hit data stream, producing trigger primitives containing elaborate physics information—e.g., the number of charged particles in a physics event—that L0TP+ can use to improve trigger decision efficiency. Deployed on a single FPGA, the system combines classical online processing with a compact Neural Network algorithm to achieve efficient event classification while managing the challenging ∼10 MHz throughput requirement of NA62. The streaming pipeline ensures ∼1 μs latency, comparable to that of the NA62 detectors, allowing its seamless integration in the existing TDAQ setup as an additional detector. Development leverages High-Level Synthesis (HLS) and the open-source hls4ml package software–hardware codesign workflow, enabling fast and flexible reprogramming, debugging, and performance optimization. We describe the implementation of the full processing pipeline, the Neural Network classifier, their functional validation, performance metrics and the system’s current status and outlook.

FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment utilizing Artificial Intelligence (AI) techniques. Integrated between the readout of the Ring Imaging Cherenkov detector (RICH) and the low-level trigger processor (L0TP+), FPGA-RICH implements a fast pipeline to process in real-time the RICH raw hit data stream, producing trigger-primitives containing elaborate physics information, such as the number of charged particles in a physics event, that L0TP+ can use to improve trigger decision selectivity. An AI algorithm provides classification of events by the number of charged particles ( N r ) with efficiency 83% and purity 85% averaged over four N r classes (0, 1, 2, >=3). The full pipeline throughput has been estimated to be above 9.375 MHz using synthetic data, and the system has been integrated in parasitic mode at NA62 to complete validation at the full experiment event rate of 10 MHz.

The NA62 experiment is designed to study rare and ultra-rare kaon decays using a decay-in-flight technique. The Trigger and Data Acquisition (TDAQ) system of NA62 is multi-level, making it critically dependent on the performance of the inter-level network. To manage the huge amount of data produced by the detectors, three levels of triggers are employed. The first level L0TP, implemented using an FPGA device, has been in operation since the start of data taking in 2016. In order to increase the efficiency of the system and implement additional algorithms, an upgraded system (L0TP+) was developed starting in 2018. This upgrade avails itself of a high-end FPGA available on the market, offering more computing power, larger local memory and higher transmission bandwidth. We have planned tests for a new trigger algorithm that implements quadrant-based logic for the veto systems. This new approach is expected to improve the main trigger efficiency by several percent. Extensive tests were conducted using a parasitic setup that included a set of Network TAPs and a commodity server, allowing for proficient comparison of trigger decisions on an event-by-event basis. The experience gained from this parasitic mode operation can be leveraged for the next data-taking period as a development setup to implement additional features, thereby accelerating the TDAQ upgrade. After the testing period, the new system has been adopted as the online processor since 2023. Preliminary results on the efficiency of the new system will be reported. Integration with the new AI-based FPGA-RICH system, which performs online partial particle identification, will also be discussed.

The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 10 12 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.

A sample of 1.69 × 107 fully reconstructed π0 → γe+e− in the kinematic range mee > 10MeV/c2 with a negligible background contamination collected by the NA48/2 experiment at CERN in 2003-04 is analysed to search for the dark photon (A′) via the decay chain π;0 → γA′, A′ → e+e. No signal is observed, and preliminary exclusion limits on space of dark photon mass mA′ and mixing parameter ϵ2 are reported.

Usage of Graphics Processing Units (GPUs) in the so called general-purpose computing is emerging as an effective approach in several fields of science, although so far applications have been employing GPUs typically for offline computations. Taking into account the steady performance increase of GPU architectures in terms of computing power and I/O capacity, the real-time applications of these devices can thrive in high-energy physics data acquisition and trigger systems. We will examine the use of online parallel computing on GPUs for the synchronous low-level trigger, focusing on tests performed on the trigger system of the CERN NA62 experiment. To successfully integrate GPUs in such an online environment, latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Furthermore, it is assessed how specific trigger algorithms can be parallelized and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen Large Hadron Collider (LHC) luminosity upgrade where highly selective algorithms will be essential to maintain sustainable trigger rates with very high pileup.

A sample of1.3 × 10⁵ K⁺ → π⁰ e⁺ ν γcandidates with less than 1% background was collected by the NA62 experiment at the CERN SPS in 2017-2018. Branching fraction measurements are obtained at percent relative precision in three restricted kinematic regions, improving on existing results by a factor larger than two. An asymmetry, possibly related to T-violation, is investigated with no evidence observed within the achieved precision.

A sample of 2.8 × 10 ⁴ K ⁺→ π ⁺ μ ⁺ μ ⁻candidates with negligible background was collected by the NA62 experiment at the CERN SPS in 2017–2018. The model-independent branching fraction is measured to be (9.15 ± 0.08) × 10 ⁻⁸ , a factor three more precise than previous measurements. The decay form factor is presented as a function of the squared dimuon mass. A measurement of the form factor parameters and their uncertainties is performed using a description based on Chiral Perturbation Theory at 𝓞 (p ⁶ ).

We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.