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Today, the introduction of wide band gap (WBG) semiconductors in power electronics has become mandatory to improve the energy efficiency of devices and modules and to reduce the overall electric power consumption in the world. Due to its excellent properties, gallium nitride (GaN) and related alloys (e.g., AlxGa1−xN) are promising semiconductors for the next generation of high-power and high-frequency devices. However, there are still several technological concerns hindering the complete exploitation of these materials. As an example, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are inherently normally-on devices. However, normally-off operation is often desired in many power electronics applications. This review paper will give a brief overview on some scientific and technological aspects related to the current normally-off GaN HEMTs technology. A special focus will be put on the p-GaN gate and on the recessed gate hybrid metal insulator semiconductor high electron mobility transistor (MISHEMT), discussing the role of the metal on the p-GaN gate and of the insulator in the recessed MISHEMT region. Finally, the advantages and disadvantages in the processing and performances of the most common technological solutions for normally-off GaN transistors will be summarized.

This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

Silicon carbide (4H-SiC) Schottky diodes have reached a mature level of technology and are today essential elements in many applications of power electronics. In this context, the study of Schottky barriers on 4H-SiC is of primary importance, since a deeper understanding of the metal/4H-SiC interface is the prerequisite to improving the electrical properties of these devices. To this aim, over the last three decades, many efforts have been devoted to developing the technology for 4H-SiC-based Schottky diodes. In this review paper, after a brief introduction to the fundamental properties and electrical characterization of metal/4H-SiC Schottky barriers, an overview of the best-established materials and processing for the fabrication of Schottky contacts to 4H-SiC is given. Afterwards, besides the consolidated approaches, a variety of nonconventional methods proposed in literature to control the Schottky barrier properties for specific applications is presented. Besides the possibility of gaining insight into the physical characteristics of the Schottky contact, this subject is of particular interest for the device makers, in order to develop a new class of Schottky diodes with superior characteristics.

Semiconducting transition metal dichalcogenides (TMDs) are promising materials for future electronic and optoelectronic applications. However, their electronic properties are strongly affected by peculiar nanoscale defects/inhomogeneities (point or complex defects, thickness fluctuations, grain boundaries, etc.), which are intrinsic of these materials or introduced during device fabrication processes. This paper reviews recent applications of conductive atomic force microscopy (C-AFM) to the investigation of nanoscale transport properties in TMDs, discussing the implications of the local phenomena in the overall behavior of TMD-based devices. Nanoscale resolution current spectroscopy and mapping by C-AFM provided information on the Schottky barrier uniformity and shed light on the mechanisms responsible for the Fermi level pinning commonly observed at metal/TMD interfaces. Methods for nanoscale tailoring of the Schottky barrier in MoS2 for the realization of ambipolar transistors are also illustrated. Experiments on local conductivity mapping in monolayer MoS2 grown by chemical vapor deposition (CVD) on SiO2 substrates are discussed, providing a direct evidence of the resistance associated to the grain boundaries (GBs) between MoS2 domains. Finally, C-AFM provided an insight into the current transport phenomena in TMD-based heterostructures, including lateral heterojunctions observed within MoxW1–xSe2 alloys, and vertical heterostructures made by van der Waals stacking of different TMDs (e.g., MoS2/WSe2) or by CVD growth of TMDs on bulk semiconductors.

The book \"Nitride Semiconductor Technology\" provides an overview of nitride semiconductors and their uses in optoelectronics and power electronics devices.It explains the physical properties of those materials as well as their growth methods.

Wide bandgap (WBG) semiconductors are becoming more widely accepted for use in power electronics due to their superior electrical energy efficiencies and improved power densities. Although WBG cubic silicon carbide (3C-SiC) displays a modest bandgap compared to its commercial counterparts (4H-silicon carbide and gallium nitride), this material has excellent attributes as the WBG semiconductor of choice for low-resistance, reliable diode and MOS devices. At present the material remains firmly in the research domain due to numerous technological impediments that hamper its widespread adoption. The most obvious obstacle is defect-free 3C-SiC; presently, 3C-SiC bulk and heteroepitaxial (on-silicon) display high defect densities such as stacking faults and antiphase boundaries. Moreover, heteroepitaxy 3C-SiC-on-silicon means low temperature processing budgets are imposed upon the system (max. temperature limited to ~1400 °C) limiting selective doping realisation. This paper will give a brief overview of some of the scientific aspects associated with 3C-SiC processing technology in addition to focussing on the latest state of the art results. A particular focus will be placed upon key process steps such as Schottky and ohmic contacts, ion implantation and MOS processing including reliability. Finally, the paper will discuss some device prototypes (diodes and MOSFET) and draw conclusions around the prospects for 3C-SiC devices based upon the processing technology presented.

Two-dimensional (2D) materials, such as graphene (Gr), transition metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN), offer interesting opportunities for the implementation of vertical transistors for digital and high-frequency electronics. This paper reviews recent developments in this field, presenting the main vertical device architectures based on 2D/2D or 2D/3D material heterostructures proposed so far. For each of them, the working principles and the targeted application field are discussed. In particular, tunneling field effect transistors (TFETs) for beyond-CMOS low power digital applications are presented, including resonant tunneling transistors based on Gr/h-BN/Gr stacks and band-to-band tunneling transistors based on heterojunctions of different semiconductor layered materials. Furthermore, recent experimental work on the implementation of the hot electron transistor (HET) with the Gr base is reviewed, due to the predicted potential of this device for ultra-high frequency operation in the THz range. Finally, the material sciences issues and the open challenges for the realization of 2D material-based vertical transistors at a large scale for future industrial applications are discussed.

Atomic layer deposition (ALD) of high-κ dielectrics on two-dimensional (2D) materials (including graphene and transition metal dichalcogenides) still represents a challenge due to the lack of out-of-plane bonds on the pristine surfaces of 2D materials, thus making the nucleation process highly disadvantaged. The typical methods to promote the nucleation (i.e., the predeposition of seed layers or the surface activation via chemical treatments) certainly improve the ALD growth but can affect, to some extent, the electronic properties of 2D materials and the interface with high-κ dielectrics. Hence, direct ALD on 2D materials without seed and functionalization layers remains highly desirable. In this context, a crucial role can be played by the interaction with the substrate supporting the 2D membrane. In particular, metallic substrates such as copper or gold have been found to enhance the ALD nucleation of Al2O3 and HfO2 both on monolayer (1 L) graphene and MoS2. Similarly, uniform ALD growth of Al2O3 on the surface of 1 L epitaxial graphene (EG) on SiC (0001) has been ascribed to the peculiar EG/SiC interface properties. This review provides a detailed discussion of the substrate-driven ALD growth of high-κ dielectrics on 2D materials, mainly on graphene and MoS2. The nucleation mechanism and the influence of the ALD parameters (namely the ALD temperature and cycle number) on the coverage as well as the structural and electrical properties of the deposited high-κ thin films are described. Finally, the open challenges for applications are discussed.

Molybdenum disulphide (MoS2) is currently regarded as a promising material for the next generation of electronic and optoelectronic devices. However, several issues need to be addressed to fully exploit its potential for field effect transistor (FET) applications. In this context, the contact resistance, R C, associated with the Schottky barrier between source/drain metals and MoS2 currently represents one of the main limiting factors for suitable device performance. Furthermore, to gain a deeper understanding of MoS2 FETs under practical operating conditions, it is necessary to investigate the temperature dependence of the main electrical parameters, such as the field effect mobility (μ) and the threshold voltage (V th). This paper reports a detailed electrical characterization of back-gated multilayer MoS2 transistors with Ni source/drain contacts at temperatures from T = 298 to 373 K, i.e., the expected range for transistor operation in circuits/systems, considering heating effects due to inefficient power dissipation. From the analysis of the transfer characteristics (I D−V G) in the subthreshold regime, the Schottky barrier height (ΦB ≈ 0.18 eV) associated with the Ni/MoS2 contact was evaluated. The resulting contact resistance in the on-state (electron accumulation in the channel) was also determined and it was found to increase with T as R C proportional to T 3.1. The contribution of R C to the extraction of μ and V th was evaluated, showing a more than 10% underestimation of μ when the effect of R C is neglected, whereas the effect on V th is less significant. The temperature dependence of μ and V th was also investigated. A decrease of μ proportional to 1/T α with α = 1.4 ± 0.3 was found, indicating scattering by optical phonons as the main limiting mechanism for mobility above room temperature. The value of V th showed a large negative shift (about 6 V) increasing the temperature from 298 to 373 K, which was explained in terms of electron trapping at MoS2/SiO2 interface states.

Due to its excellent physical properties and availability directly on a semiconductor substrate, epitaxial graphene (EG) grown on the (0001) face of hexagonal silicon carbide is a material of choice for advanced applications in electronics, metrology and sensing. The deposition of ultrathin high-k insulators on its surface is a key requirement for the fabrication of EG-based devices, and, in this context, atomic layer deposition (ALD) is the most suitable candidate to achieve uniform coating with nanometric thickness control. This paper presents an overview of the research on ALD of high-k insulators on EG, with a special emphasis on the role played by the peculiar electrical/structural properties of the EG/SiC (0001) interface in the nucleation step of the ALD process. The direct deposition of Al2O3 thin films on the pristine EG surface will be first discussed, demonstrating the critical role of monolayer EG uniformity to achieve a homogeneous Al2O3 coverage. Furthermore, the ALD of several high-k materials on EG coated with different seeding layers (oxidized metal films, directly deposited metal-oxides and self-assembled organic monolayers) or subjected to various prefunctionalization treatments (e.g., ozone or fluorine treatments) will be presented. The impact of the pretreatments and of thermal ALD growth on the defectivity and electrical properties (doping and carrier mobility) of the underlying EG will be discussed.