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Single-photon sources are important for integrated photonics and quantum technologies, and can be used in quantum key distribution, quantum computing, and sensing. Color centers in the solid state are a promising candidate for the development of the next generation of single-photon sources integrated in quantum photonics devices. They are point defects in a crystal lattice that absorb and emit light at given wavelengths and can emit single photons with high efficiency. The landscape of color centers has changed abruptly in recent years, with the identification of a wider set of color centers and the emergence of new solid-state platforms for room-temperature single-photon generation. This review discusses the emerging material platforms hosting single-photon-emitting color centers, with an emphasis on their potential for the development of integrated optical circuits for quantum photonics.

Since the 1980s, researchers have taken giant steps in understanding how to use quantum mechanics for solving real problems—for example, making a computer that works according to the laws of quantum mechanics. In recent decades, researchers have tried to develop a platform for quantum information and computation that can be integrated into digital and telecom technologies without the need of a cryogenic environment. The current status of research in the field of quantum integrated photonics will be reviewed. A review of the most common integrated photonic platforms will be given, together with the main achievements and results in the last decade.

Integrated photonic platforms have rapidly emerged as highly promising and extensively investigated systems for advancing classical and quantum information technologies, since their ability to seamlessly integrate photonic components within the telecommunication band with existing silicon-based industrial processes offers significant advantages. However, despite this integration facilitating the development of novel devices, fostering fast and reliable communication protocols and the manipulation of quantum information, traditional integrated silicon photonics faces inherent physical limitations that necessitate a challenging trade-off between device efficiency and spatial footprint. To address this issue, researchers are focusing on the integration of nanoscale materials into photonic platforms, offering a novel approach to enhance device performance while reducing spatial requirements. These developments are of paramount importance in both classical and quantum information technologies, potentially revolutionizing the industry. In this review, we explore the latest endeavors in hybrid photonic platforms leveraging the combination of integrated silicon photonic platforms and nanoscale materials, allowing for the unlocking of increased device efficiency and compact form factors. Finally, we provide insights into future developments and the evolving landscape of hybrid integrated photonic nanomaterial platforms.

The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 10 12 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and focus of the project; nevertheless, the final design will include additional features, such as a PCIe RDMA engine to enable processing on CPU and GPU accelerators, and the partial reconfiguration of trigger firmware starting from a high level language description (C/C++). The latter capability is enabled by modern High Level Synthesis (HLS) tools, but to what extent this methodology can be applied to perform complex tasks in the L0 trigger, with its stringent latency requirements and the limits imposed by single FPGA resources, is currently being investigated. As a test case for this scenario we considered the online reconstruction of the RICH detector rings on an HLS generated module, using a dedicated primitives data stream with PM hits IDs. Besides, the chosen platform supports the Virtex Ultrascale+ FPGA wide I/O capabilities, allowing for straightforward integration of primitive streams from additional sub-detectors in order to improve the performance of the trigger.

We numerically investigated the use of graphene nanoribbons placed on top of silicon-on-insulator (SOI) strip waveguides for light polarization control in silicon photonic-integrated waveguides. We found that two factors mainly affected the polarization control: the graphene chemical potential and the geometrical parameters of the waveguide, such as the waveguide and nanoribbon widths and distance. We show that the graphene chemical potential influences both TE and TM polarizations almost in the same way, while the waveguide width tapering enables both TE-pass and TM-pass polarizing functionalities. Overall, by increasing the oxide spacer thickness between the silicon waveguide and the top graphene layer, the device insertion losses can be reduced, while preserving a high polarization extinction ratio.

Photon Number Resolving Detectors (PNRDs) are devices capable of measuring the number of photons present in an incident optical beam, enabling light sources to be measured and characterized at the quantum level. In this paper, we explore the performance and design considerations of a linearly multiplexed photon number-resolving single-photon detector array, integrated on a single mode waveguide. Our investigation focus on defining and analyzing the fidelity of such an array under various conditions and proposing practical designs for its implementation. Through theoretical analysis and numerical simulations, we show how propagation losses and dark counts may have a strong impact on the performance of the system and highlight the importance of mitigating these effects in practical implementations.

The NA62 experiment at CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K+ -> pi+ nu nubar collecting O(100) events with a 10% background to make a stringent test of the Standard Model. One of the main backgrounds to the proposed measurement is represented by the K+ -> pi+ pi0 decay. To suppress this background an efficient photo veto system is foreseen. In the 1-10 mrad angular region the NA48 high performance liquid krypton electromagnetic calorimeter is used. The design, implementation and current status of the Liquid Krypton Electromagnetic Calorimeter Level 0 Trigger are presented.

We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design allows us to build a low latency, high bandwidth PC cluster, the APEnet+ network, the new generation of our cost-effective, tens-of-thousands-scalable cluster network architecture. Some test results and characterization of data transmission of a complete testbench, based on a commercial development card mounting an Altera FPGA, are provided.

Many scientific computations need multi-node parallelism for matching up both space (memory) and time (speed) ever-increasing requirements. The use of GPUs as accelerators introduces yet another level of complexity for the programmer and may potentially result in large overheads due to the complex memory hierarchy. Additionally, top-notch problems may easily employ more than a Petaflops of sustained computing power, requiring thousands of GPUs orchestrated with some parallel programming model. Here we describe APEnet+, the new generation of our interconnect, which scales up to tens of thousands of nodes with linear cost, thus improving the price/performance ratio on large clusters. The project target is the development of the Apelink+ host adapter featuring a low latency, high bandwidth direct network, state-of-the-art wire speeds on the links and a PCIe X8 gen2 host interface. It features hardware support for the RDMA programming model and experimental acceleration of GPU networking. A Linux kernel driver, a set of low-level RDMA APIs and an OpenMPI library driver are available, allowing for painless porting of standard applications. Finally, we give an insight of future work and intended developments.

Floods are extreme hydrological events that can reshape the landscape, transform entire ecosystems and alter the relationship between living organisms and the surrounding environment. Every year, fluvial and coastal floods claim thousands of human lives and cause enormous direct damages and inestimable indirect losses, particularly in less developed and more vulnerable regions. Monitoring the spatiotemporal evolution of floods is fundamental to reducing their devastating consequences. Observing floods from space can make the difference: from this distant vantage point it is possible to monitor vast areas consistently, and, by leveraging multiple sensors on different satellites, it is possible to acquire a comprehensive overview on the evolution of floods at a large scale. Synthetic aperture radar (SAR) sensors, in particular, have proven extremely effective for flood monitoring, as they can operate day and night and in all weather conditions, with a highly discriminatory power. On the other hand, SAR sensors are unable to reliably detect water in some cases, the most critical being urban areas. Furthermore, flood water depth – which is a fundamental variable for emergency response and impact calculations – cannot be estimated remotely. In order to address such limitations, this study proposes a framework for estimating flood water depths and enhancing flood delineations, based on readily available topographical data. The methodology is specifically designed to accommodate, as additional inputs, masks delineating water bodies and/or no-data areas. In particular, the method relies on simple morphological arguments to expand flooded areas into no-data regions and to estimate water depths based on the terrain elevation of the boundaries between flooded and non-flooded areas. The underlying algorithm – named FLEXTH – is provided as Python code and is designed to run in an unsupervised mode in a reasonable time over areas of several hundred thousand square kilometers. This new tool aims to quantify and ultimately to reduce the impacts of floods, especially when used in synergy with the recently released Global Flood Monitoring product of the Copernicus Emergency Management Service.