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In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

This paper presents a physics-based compact model able to describe the time dynamics of the erase operation in three-dimensional NAND Flash strings exploiting gate-induced drain leakage at the selector to increase the string potential. The model accurately reproduces all the main phases of the erase operation and allows to calculate the threshold voltage transient arising from hole injection into and electron emission from the gate stack of the memory cells, accounting for the correct cylindrical geometry of the string. Thanks to its simple structure, the model is suitable for parametric analyses aiming at optimizing the string structure and the operating waveforms from the standpoint of the erase performance.

In this paper, the impact of moisture on the time‐dependent dielectric breakdown (TDDB) in polymeric dielectrics for galvanic isolators is investigated experimentally. Through ad hoc test schemes, device lifetime under electrical stress is quantitatively correlated to the moisture concentration in the samples by monitoring the latter via the permittivity of the dielectric material. Experimental data reveal that TDDB shows a strongly nonlinear dependence on moisture concentration, with device lifetime displaying, first, a strong decrease with the increase in it and, then, a net saturation. This behaviour is observed for different temperatures of the stress phase and the temperature activation of device lifetime appears to be independent of the moisture concentration. Finally, a sound physical picture is proposed to explain all the experimental evidence, allowing to get insights into the role of moisture in the TDDB of galvanic isolators based on polymeric dielectrics.

In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 amplifiers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 amplifiers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufficiently high data quality to allow for single neuron identification (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1:25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0:35 µm AMS CMOS process featuring a 3 V power supply with an area of 3:1 x 2:7 mm2. The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17:2 mW. This figure translates into a power budget of 269 µW per channel, in line with published results but allowing a larger transmission distance and more efficient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings.