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34 result(s) for "Trainor, Nicholas"
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Three-dimensional integration of two-dimensional field-effect transistors
In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as ‘More Moore’ 1 but also introduces multifunctionalities for ‘More than Moore’ 2 technologies. Although silicon-based 3D integrated circuits are commercially available 3 – 5 , there is limited effort on 3D integration of emerging nanomaterials 6 , 7 such as two-dimensional (2D) materials despite their unique functionalities 7 – 10 . Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS 2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS 2 and WSe 2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS 2 FETs (channel length, L CH  = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension. Monolithic three-dimensional integration of two-dimensional field-effect transistors enables improved integration density and multifunctionality to realize ‘More Moore’ and ‘More than Moore’ technologies.
All-in-one, bio-inspired, and low-power crypto engines for near-sensor security based on two-dimensional memtransistors
In the emerging era of the internet of things (IoT), ubiquitous sensors continuously collect, consume, store, and communicate a huge volume of information which is becoming increasingly vulnerable to theft and misuse. Modern software cryptosystems require extensive computational infrastructure for implementing ciphering algorithms, making them difficult to be adopted by IoT edge sensors that operate with limited hardware resources and at low energy budgets. Here we propose and experimentally demonstrate an “all-in-one” 8 × 8 array of robust, low-power, and bio-inspired crypto engines monolithically integrated with IoT edge sensors based on two-dimensional (2D) memtransistors. Each engine comprises five 2D memtransistors to accomplish sensing and encoding functionalities. The ciphered information is shown to be secure from an eavesdropper with finite resources and access to deep neural networks. Our hardware platform consists of a total of 320 fully integrated monolayer MoS 2 -based memtransistors and consumes energy in the range of hundreds of picojoules and offers near-sensor security. Internet of things (IoT) sensors can collect, store and communicate large volumes of information, which require effective security measures. Here, the authors report the realization of low-power edge sensors based on photosensitive and programmable 2D memtransistors, integrating sensing, storage and encryption functionalities.
Hardware implementation of Bayesian network based on two-dimensional memtransistors
Bayesian networks (BNs) find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc. The basic computing primitive for BNs is a stochastic bit (s-bit) generator that can control the probability of obtaining ‘1’ in a binary bit-stream. While silicon-based complementary metal-oxide-semiconductor (CMOS) technology can be used for hardware implementation of BNs, the lack of inherent stochasticity makes it area and energy inefficient. On the other hand, memristors and spintronic devices offer inherent stochasticity but lack computing ability beyond simple vector matrix multiplication due to their two-terminal nature and rely on extensive CMOS peripherals for BN implementation, which limits area and energy efficiency. Here, we circumvent these challenges by introducing a hardware platform based on 2D memtransistors. First, we experimentally demonstrate a low-power and compact s-bit generator circuit that exploits cycle-to-cycle fluctuation in the post-programmed conductance state of 2D memtransistors. Next, the s-bit generators are monolithically integrated with 2D memtransistor-based logic gates to implement BNs. Our findings highlight the potential for 2D memtransistor-based integrated circuits for non-von Neumann computing applications. Bayesian networks are applied to resolve several types of probabilistic problems. Here, Das et al. develop a stochastic computing hardware platform using two-dimensional memtransistors for the implementation of Bayesian network with high accuracy.
Active pixel sensor matrix based on monolayer MoS2 phototransistor array
In-sensor processing, which can reduce the energy and hardware burden for many machine vision applications, is currently lacking in state-of-the-art active pixel sensor (APS) technology. Photosensitive and semiconducting two-dimensional (2D) materials can bridge this technology gap by integrating image capture (sense) and image processing (compute) capabilities in a single device. Here, we introduce a 2D APS technology based on a monolayer MoS 2 phototransistor array, where each pixel uses a single programmable phototransistor, leading to a substantial reduction in footprint (900 pixels in ∼0.09 cm 2 ) and energy consumption (100s of fJ per pixel). By exploiting gate-tunable persistent photoconductivity, we achieve a responsivity of ∼3.6 × 10 7  A W −1 , specific detectivity of ∼5.6 × 10 13  Jones, spectral uniformity, a high dynamic range of ∼80 dB and in-sensor de-noising capabilities. Further, we demonstrate near-ideal yield and uniformity in photoresponse across the 2D APS array. Low-power and compact active pixel sensor (APS) matrices are desired for resource-limited edge devices. Here, the authors report a small-footprint APS matrix based on monolayer MoS 2 phototransistors arrays exhibiting spectral uniformity, reconfigurable photoresponsivity and de-noising capabilities at low energy consumption.
Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors
Three-dimensional monolithic integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrent with enhanced energy efficiency in big data applications such as artificial intelligence. Despite decades of efforts, there remains an urgent need for reliable, compact, fast, energy-efficient and scalable memory devices. Ferroelectric field-effect transistors (FE-FETs) are a promising candidate, but requisite scalability and performance in a back-end-of-line process have proven challenging. Here we present back-end-of-line-compatible FE-FETs using two-dimensional MoS 2 channels and AlScN ferroelectric materials, all grown via wafer-scalable processes. A large array of FE-FETs with memory windows larger than 7.8 V, ON/OFF ratios greater than 10 7 and ON-current density greater than 250 μA um –1 , all at ~80 nm channel length are demonstrated. The FE-FETs show stable retention up to 10 years by extension, and endurance greater than 10 4  cycles in addition to 4-bit pulse-programmable memory features, thereby opening a path towards the three-dimensional heterointegration of a two-dimensional semiconductor memory with silicon complementary metal–oxide–semiconductor logic. A large array of ferroelectric field-effect transistors with record memory windows, ON/OFF ratios and ON-current density is presented at ~80 nm channel length.
Two-dimensional materials-based probabilistic synapses and reconfigurable neurons for measuring inference uncertainty using Bayesian neural networks
Artificial neural networks have demonstrated superiority over traditional computing architectures in tasks such as pattern classification and learning. However, they do not measure uncertainty in predictions, and hence they can make wrong predictions with high confidence, which can be detrimental for many mission-critical applications. In contrast, Bayesian neural networks (BNNs) naturally include such uncertainty in their model, as the weights are represented by probability distributions (e.g. Gaussian distribution). Here we introduce three-terminal memtransistors based on two-dimensional (2D) materials, which can emulate both probabilistic synapses as well as reconfigurable neurons. The cycle-to-cycle variation in the programming of the 2D memtransistor is exploited to achieve Gaussian random number generator-based synapses, whereas 2D memtransistor based integrated circuits are used to obtain neurons with hyperbolic tangent and sigmoid activation functions. Finally, memtransistor-based synapses and neurons are combined in a crossbar array architecture to realize a BNN accelerator for a data classification task. Designing efficient Bayesian neural networks remains a challenge. Here, the authors use the cycle variation in the programming of the 2D memtransistors to achieve Gaussian random number generator-based synapses, and combine it with the complementary 2D memtransistors-based tanh function to implement a Bayesian neural network.
Step engineering for nucleation and domain orientation control in WSe2 epitaxy on c-plane sapphire
Epitaxial growth of two-dimensional transition metal dichalcogenides on sapphire has emerged as a promising route to wafer-scale single-crystal films. Steps on the sapphire act as sites for transition metal dichalcogenide nucleation and can impart a preferred domain orientation, resulting in a substantial reduction in mirror twins. Here we demonstrate control of both the nucleation site and unidirectional growth direction of WSe 2 on c -plane sapphire by metal–organic chemical vapour deposition. The unidirectional orientation is found to be intimately tied to growth conditions via changes in the sapphire surface chemistry that control the step edge location of WSe 2 nucleation, imparting either a 0° or 60° orientation relative to the underlying sapphire lattice. The results provide insight into the role of surface chemistry on transition metal dichalcogenide nucleation and domain alignment and demonstrate the ability to engineer domain orientation over wafer-scale substrates. Surface chemistry controls the location of WSe 2 nucleation on a stepped sapphire substrate. Preferential nucleation at either the top or bottom step edge can be used to minimize mirror twin domains and produce unidirectional WSe 2 monolayers.
Two-dimensional-materials-based transistors using hexagonal boron nitride dielectrics and metal gate electrodes with high cohesive energy
Two-dimensional (2D) semiconductors could potentially be used as channel materials in commercial field-effect transistors. However, the interface between 2D semiconductors and most gate dielectrics contains traps that degrade performance. Layered hexagonal boron nitride (h-BN) can form a defect-free interface with 2D semiconductors, but when prepared by industry-compatible methods—such as chemical vapour deposition (CVD)—the presence of native defects increases leakage current and reduces dielectric strength. Here we show that metal gate electrodes with a high cohesive energy—platinum and tungsten—can allow CVD-grown layered h-BN to be used as a gate dielectric in transistors. The electrodes can reduce the current across CVD-grown h-BN by a factor of around 500 compared to similar devices with gold electrodes and can provide a high dielectric strength of at least 25 MV cm −1 . We examine the behaviour statistically across 867 devices, which includes a microchip based on complementary metal–oxide–semiconductor technology. Metal gate electrodes with a high cohesive energy—platinum and tungsten—can be used to mitigate leakage currents and premature dielectric breakdown across chemical vapour deposition-grown multilayer hexagonal boron nitride, allowing the material to be used as a gate dielectric in two-dimensional-materials-based transistors.
Survey of Etching Techniques to Produce Cr2C MXene from Cr2AlC
Two-dimensional chromium carbide MXene (Cr2CTX) is predicted to possess a high hydrogen capacity and antiferromagentism which may be employed in hydrogen storage and spintronic applications. As of the time of the work detailed in this thesis, there have not yet been any reported success synthesis of Cr2CTX. Herein is a systematic survey of different possible etching conditions to produce Cr2CTX from Cr2AlC. Three distinct etching techniques previously used to synthesize MXenes were studied. Wet etchings were conducted using either hydrofluoric acid along with sulfuric and hydrochloric acid or hydrochloric acid with fluoride salts. HF/HCl and KF/HCl were the most promising etchants, producing XRD peaks consistent with MXenes. Importantly, samples produced using the wet etchants often contained both unreacted MAX and degradation products, such as CrO3, demonstrating that chromium and aluminum are being etched at comparable rates, preventing the formation of the desired MXene. Additionally, a molten salt technique using zinc chloride was also studied by varying the time and ratio of reagents. This technique also hold promise with several samples possessing XRD peaks consistent with Cr2CTX. Additionally, the lack of chromium chlorides and presence of zinc chromite indicate that MXene degradation is due to oxygen in the system rather than the molten salt treatment itself.