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The potential of all‐inorganic halide perovskite‐based memristors as a solution to the limitations of traditional memory systems, particularly in the context of edge computing and next‐generation digital architectures, is investigated. The rapid expansion of data‐driven applications demands more efficient, secure, and scalable memory technologies, prompting this exploration of memristors for their unique resistance‐switching properties. The research aims to address the challenges of data security and processing efficiency by integrating memristors into logic circuits, enabling both memory and logic operations within a single device. The study is structured around the experimental fabrication and characterization of Cs3Bi2I6Br3 perovskite memristors. A simple solution‐processed spin coating method with antisolvent‐assisted crystallization was employed to fabricate the memristor devices. The experimental characterization of memristors, including X‐ray diffraction (XRD) analysis and electrical measurements, confirmed their structural integrity and memristive behavior, with distinct hysteresis loops indicative of nonvolatile memory properties. To analyze the behavior of the memristors in electronic circuits, a Verilog‐A mathematical model was developed, and simulations were conducted using the Cadence Virtuoso Electronic Design Automation (EDA) suite. The Verilog‐A model demonstrates strong agreement with measured results and validates the device's hysteresis behavior. Key findings demonstrate that metal halide perovskite (MHP) memristors exhibit excellent switching characteristics, repeatability, and integration potential with complementary metal‐oxide‐semiconductor (CMOS) technology. These properties make them suitable for implementing various logic gates, such as IMPLY, AND, and OR gates, as well as more complex digital circuits like multiplexers and full adders. The results highlight the feasibility of using these memristors for in‐memory computing, where both data storage and processing occur within the memory cells, significantly enhancing computing efficiency and security. The study concludes that MHP‐based memristors offer a promising path toward more compact, energy‐efficient, and secure computing architectures. As the rapid expansion of data‐driven applications calls for more efficient, secure, and scalable memory technologies, our study addresses these challenges by exploring memristors' unique resistance switching properties. Through both experimental fabrication and computer simulations, we demonstrate the feasibility of using Cs3Bi2I6Br3 perovskite memristors in logic gate designs and complex digital circuits, such as multiplexers and full adders, highlighting their suitability for in‐memory computing systems. Key findings show that metal halide perovskite memristors exhibit excellent switching characteristics, integration potential with CMOS technology, and promise for energy‐efficient, secure, and compact computing systems. The results underscore the relevance of memristor‐based architectures in addressing the limitations of traditional memory systems, especially in high‐density and low‐power applications.

Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional computing paradigms. In particular, vanadium dioxide (VO 2 ) devices are used to design autonomous non-linear oscillators from which oscillatory neural networks (ONNs) can be developed. In this work, we propose a new architecture for ONNs in which sub-harmonic injection locking (SHIL) is exploited to ensure that the phase information encoded in each neuron can only take two values. In this sense, the implementation of ONNs from neurons that inherently encode information with two-phase values has advantages in terms of robustness and tolerance to variability present in VO 2 devices. Unlike conventional interconnection schemes, in which the sign of the weights is coded in the value of the resistances, in our proposal the negative (positive) weights are coded using static inverting (non-inverting) logic at the output of the oscillator. The operation of the proposed architecture is shown for pattern recognition applications.

Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data deluge gap”). This has resulted in investigating novel computing paradigms and design approaches at all levels from materials to system-level implementations and applications. An alternative computing approach based on artificial neural networks uses oscillators to compute or Oscillatory Neural Networks (ONNs). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. Here, we address a fundamental problem: can we efficiently perform artificial intelligence applications with ONNs? We present a digital ONN implementation to show a proof-of-concept of the ONN approach of “computing-in-phase” for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5 × 3 and 10 × 6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.