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The ever-increasing demand for faster computing has led us to an era of heterogeneous integration, where interposers and package substrates have become essential components for further performance scaling. High-bandwidth connections are needed for faster communication between logic and memory dies. There are several limitations to current generation technologies, and dielectric buildup layers are a key part of addressing those issues. Although there are several polymer dielectrics available commercially, there are numerous challenges associated with incorporating them into interposers or package substrates. This article reviewed the properties of polymer dielectric materials currently available, their properties, and the challenges associated with their fabrication, electrical performance, mechanical reliability, and electrical reliability. The current state-of-the-art is discussed, and guidelines are provided for polymer dielectrics for the next-generation interposers.

In this paper, package integration of glass–based passive components for 5G new radio (NR) millimeter–wave (mm wave) bands and an analysis of their system performance are presented. Passive components such as diplexers and couplers covering 5G NR mm wave bands n257, n258 and n260 are modeled, designed, fabricated and characterized individually along with their integrated versions. Non–contiguous diplexers are designed using three different types of filters, hairpin, interdigital and edge–coupled, and combined with a broadband coupler to emulate a power detection and control circuitry block in an RF transmitter chain. A panel–compatible semi–additive patterning (SAP) process is utilized to form high–precision redistribution layers (RDLs) on laminated glass substrate, onto which fine features with tight tolerance are added to fabricate these structures. The diplexers exhibit low insertion loss, low VSWR and high isolation, and have a small footprint. A system performance analysis using a co–simulation technique is presented for the first time to quantify the distortion in amplitude and phase produced by the fabricated passive component block in terms of error vector magnitude (EVM). Moreover, the scalability of this approach to compare similar passive components based on their specifications and signatures using a system–level performance metric such as EVM is discussed.

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Integral passives are becoming increasingly important in realizing next generation electronics industry needs through gradual replacement of discretes. The need for integral passives emerges from the increasing consumer demand for product miniaturization thus requiring components to be smaller and packaging to be space efficient. In this paper, the feasibility of integration of polymer/ceramic thin film (5 μm thick) capacitors (C) with other passive components such as resistors (R) and inductors (L) has been discussed. An integrated RC network requiring relatively large capacitance and resistance is selected as a model for co-integration of R and C components using low temperature PWB compatible fabrication processes. This test vehicle is a subset of a large electrical circuit of a functional medical device. In order to produce higher capacitance density and reduce in-plane device area, multi-layer (currently two-layer) capacitors are stacked in the thickness direction. A commercially available Ohmega-Ply resistor/conductor material is selected for integral resistors. Resistors were fabricated using a multi-step lithography process with the utilization of two separate masks. Bottom copper electrodes for capacitors were also defined during the resistor fabrication process. Photodefinable epoxies filled with a high permittivity ceramic powder were used for fabrication of thin film capacitors. Epoxy and ceramic powders were mixed in the required proportion and blended using a high shear apparatus. The coating solution was homogenized in a roll miller for 3 to 5 days prior to casting in order to prevent settling of the higher density ceramic particles. Capacitors were fabricated by spin-coating on the sub-etched copper electrodes. The deposited dielectric layers were dried, exposed with UV radiation, patterned, and thermally cured. Top capacitor electrodes (copper) were deposited using a metal or an e-beam evaporator. The electrodes were patterned using the standard photolithography processes. Selected good samples were used for depositing the second capacitor layer. The RC network is extended to incorporate electroplated polymer/ferrite core micro-inductors through the fabrication of an industry prototype low pass RLC filter. Meniscus coating was evaluated for large area manufacturing with high process yield. A capacitance density of 3 nF cm^sup -2^ was obtained on a single layer capacitor with 6 μm thick films. The capacitance density was increased to 6 nF cm^sup -2^ with the two-layer deposition process. The capacitors were relatively stable up to a frequency range of 120 Hz to 100 KHz. Meniscus coating was qualified to be a viable manufacturable method for depositing polymer/ceramic capacitors on large area (300mm x 300mm) PWB substrates. Dielectric constant values in the range of 3.5 to 35 with increase in filler loading up to 45 vol% were achieved in the epoxy nanocomposite system where the dielectric constant of the host polymer was limited to 3.5. Higher dielectric constant polymers are required to meet the increasingly higher capacitance needs for the next generation electronics packaging. Possible avenues for achieving higher capacitance density in polymer/ceramic nanocomposite system have been discussed.[PUBLICATION ABSTRACT]

In this study, individual interactions between various classes of organic additives in electrolytic copper plating solutions are characterized by electroanalytical methods. Cyclic voltammetry and chronopotentiometry were used to compare cases of sequential and competitive adsorption of additive combinations to the Cu cathode. Of the polyalkylene glycol (PAG) suppressors investigated, polypropylene glycol was in general a weaker suppressor than polyethylene glycol, showing weaker polarization of the Cu cathode and faster depolarization when combined with bis(sodium sulfopropyl)disulfide (SPS). The rapid depolarization of PAG with SPS resulted in a conformal Cu filling behavior in blind-vias. By itself, the leveler molecule polyvinyl pyrrolidone (PVP) shows very weak and slow suppression compared to the PAG-type suppressors, but depolarization of the Cu cathode is prevented when combined with SPS. The weak polarization of PVP combined with SPS resulted in sub-conformal filling behavior in blind-vias. The potential response of SPS, PAG, and PVP combined was found to be the sum of their individual interactions: PAG adsorbs rapidly to strongly polarize the cathode, but PVP prevents depolarization with time from SPS. This strong and consistent polarization outside the vias resulted in a superconformal filling behavior, with more than twice the thickness of Cu plated in the vias than outside.

Chemical structure and leakage properties of electrochemically grown tantalum oxide films on high-surface area tantalum were studied. Tantalum oxide films with different thicknesses were grown on sintered tantalum under potentio-dynamic conditions by modifying the anodization dwell-voltages. X-ray photoelectron spectroscopy depth-profile studies were performed to investigate the surface chemical composition and oxide species of the grown tantalum oxide. Furthermore, the strength of the dielectric film was probed by analyzing the leakage properties of the tantalum oxide of different thicknesses. Different leakage current models were used to identify the plausible defect mechanisms in anodized tantalum oxide films. A mix of the stoichiometric pentavalent oxide and non-stoichiometric sub-oxides were observed in the tantalum oxide film with a distribution gradient along the oxide growth direction. A gradual drop was observed in the content of stoichiometric phase from the oxide surface to the oxide-metal interface irrespective of the oxide thickness. The non-stoichiometric content of oxide gave rise to crystalline nature in the oxide which acted as a catalyst for leakage conduction in oxide dielectrics. The electrode-dielectric interface gave rise to various defect mechanisms which also contributed to leakage in addition to crystalline content in the oxide. To the best of the authors’ knowledge, this is the first scientific reporting on composition and structure of anodically-grown tantalum oxide films on high-surface area tantalum along with identification of mechanisms responsible for their leakage properties.

Emerging high-performance systems are driving the need for advanced packaging solutions such as 3-D integrated circuits (ICs) and 2.5-D system integration with increasing performance and reliability requirements for off-chip interconnections. Solid–liquid interdiffusion (SLID) bonding resulting in all-intermetallic joints has been proposed to extend the applicability of solders, but faces fundamental and manufacturing challenges hindering its wide adoption. This paper introduces a Cu-Sn SLID interconnection technology, aiming at stabilization of the microstructure in the Cu6Sn5 metastable phase rather than the usual stable Cu3Sn phase. This enables formation of a void-free interface yielding higher mechanical strength than standard SLID bonding, as well as significantly reducing the transition time. The metastable SLID technology retains the benefits of standard SLID with superior I/O pitch scalability, thermal stability and current handling capability, while advancing assembly manufacturability. In the proposed concept, the interfacial reaction is controlled by introducing Ni(P) diffusion barrier layers, designed to effectively isolate the metastable Cu6Sn5 phase preventing any further transformation. Theoretical diffusion and kinetic models were applied to design the Ni–Cu–Sn interconnection stack to achieve the targeted joint composition. A daisy chain test vehicle was used to demonstrate this technology as a first proof of concept. Full transition to Cu6Sn5 was successfully achieved within a minute at 260°C as confirmed by scanning electron microscope (SEM) and x-ray energy dispersive spectroscopy (XEDS) analysis. The joint composition was stable through 10× reflow, with outstanding bond strength averaging 90 MPa. The metastable SLID interconnections also showed excellent electromigration performance, surviving 500 h of current stressing at 105 A/cm2 at 150°C.

Hydrothermal processing can deposit crystalline ferroelectric films at low temperatures of less than 150°C to achieve permittivities above 100. Such a process, hence, can be attractive in integrating thin film capacitors in organic, silicon or flex substrates. However, their poor insulation strength leading to high leakage current can prevent their wide acceptance. Lattice defects such as hydroxyl groups are attributed to their high leakage currents and lower Breakdown Voltages (BDVs). With appropriate thermal treatments, majority of the OH groups can be removed, leading to improved insulation characteristics. The leakage current behavior of as-synthesized and post-baked hydrothermal thin films are analyzed with various conduction models. The room temperature I-V characteristics are attributed to a combination of ionic and Space-Charge-Limited (SCLC) conduction models for films baked at 160°C while higher baking temperatures of 350°C agree well with Poole-Frenkel type conduction, with an activation energy of 0.57 eV for the defects. The defects, which are presumably OH groups or oxygen vacancies embedded in the barium titanate lattice, act as shallow traps and the trapping and detrapping results in easier conduction. A brief perspective is provided on the suitability of such a hydrothermal thin film capacitor approach for power supply applications.

To realize embedded resistors on multilayer benzocyclobutene (BCB) either on-chip or on-board, a low-cost large format electroless process for deposition of NiP and NiWP thin-film resistors using both low-temperature (25°C) and high-temperature (90°C) baths has been developed. The electroless process exhibits uniform resistor thickness in the submicron range and offers low profile and excellent adhesion to the BCB dielectric layer. The resistor films also act as a seed layer for direct electroplating of copper traces. The NiP alloys can also be tailored to a variable temperature coefficient of resistance (TCR) with different alloy compositions. The electroless process can be adopted in the PCB manufacturing industries with no additional investment. This article is the first report on electroless plated thin film resistors on low loss BCB dielectric. [PUBLICATION ABSTRACT]

The development of boards suitable for system-on-a-package applications is described. The requirement is for line/space widths of 10 micron, with multiple layers of conducting Cu patterns with interlayer dielectrics. A good match between the thermal expansion coefficients (CTE) of the board and the silicon die is also required. It is shown that high stiffness and a CTE adjustable in the range 2-4 ppm/C would enable board fabrication and assembly without underfill. Thermal cycling of test assemblies showed that AlN exhibited suitable mechanical and thermal properties, but was considered difficult to produce in large areas, and relatively expensive. C-SiC composites manufactured using a preceramic polymer and high stiffness carbon cloth were considered to be ideal candidate materials for this application. 7 refs.