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Ordinary differential equations (ODEs) are widely used in science, engineering, and mathematics, but their numerical solution on traditional Von Neumann hardware is time- and energy-consuming, especially for high-order ODEs. Here, we present a high-concurrency memristor-based ODE solver supporting arbitrary order and three configurable modes: coarse, fine, and coarse-to-fine look-ahead, to meet diverse accuracy requirements. History-based memristor programming (HMP) accelerates device conductance programming by up to 3.29 × without compromising accuracy. The reconfigurable hardware implements coarse solver via analog compute-in-memory, fine solver via digital compute-in-memory, and coarse-to-fine solver using Parareal methods for high-concurrency numerical integration. We demonstrate its performance on exponential functions, Lorenz attractors, and three-body problems, achieving 601 × ~ 6.92 × 10 3  × speedup and 1.71 × 10 3  × ~ 3.93 × 10 3  × energy improvement over CPU/GPU, respectively, when solving the same ODE tasks. The memristor-based tri-mode solver pushes ODE solver hardware performance to a new paradigm with orders of magnitude concurrency improvements. Solving ordinary differential equations (ODE) on the von Neumann architecture normally demands a large amount of computational resources. Yu et al. build ODE solver hardware using a computing-in-memory-based implementation, showing orders of magnitude improvement in energy consumption and speedup.

Object detection, as a fundamental task in computer vision, mainly performs the classification and localization of objects in images or videos. However, traditional edge computing platforms fall short of meeting the demands for state‐of‐the‐art object detection model size and computing power. Here, a 128 Mb phase change memory chip is fabricated with a high memory yield of 99.99999% in a 40 nm node and utilized for efficient in‐memory vector‐matrix multiplication and in‐memory max computation. In particular, in order to mitigate the significant programming energy overheads for large‐scale memristor arrays and the reliance on high‐precision analog‐to‐digital‐converter (ADC) in compute‐in‐memory operations, a novel mixed‐precision weight mapping strategy is adopted. Compared with traditional schemes, the ADC modules achieve up to a 22.3× reduction in energy consumption while maintaining equivalent network performance. Ultimately, this memristive in‐memory object detection system demonstrates 4,180× higher energy efficiency and 228× greater computational throughput compared to GPU implementations. A memristive in‐memory object detection system is presented for edge computing based on a 128 Mb phase change memory chip (40 nm, 99.99999 % yield) enabling in‐memory vector‐matrix multiplication and max computation. A novel mixed‐precision weight mapping reduces analog‐to‐digital‐converter energy by 22.3×. This memristive in‐memory object detection system achieves 4,180× higher energy efficiency and 228× greater throughput than GPU implementations.

Following the publication of this article, a concerned reader drew to our attention that in Fig. 5C on p. 1704, showing histological images of mouse livers stained with H&E, unexpected areas of similarity were identified in terms of the staining patterns revealed within the data panels themselves. After having conducted an internal investigation, the Editor of has reached the conclusion that the overlapping portions of data shown in this figure were unlikely to have arisen by coincidence. Therefore, on the grounds of a lack of confidence in the integrity of these data, the Editor has decided that the article should be retracted from the publication. The authors were asked for an explanation to account for these concerns, but the Editorial Office did not receive any reply. The Editor apologizes to the readership for any inconvenience caused, and thanks the interested reader for drawing this matter to our attention. [Oncology Reports 37: 1698‑1706, 2017; DOI: 10.3892/or.2017.5382].

Liver fibrosis is a chronic liver disease characterized by the proliferation and activation of hepatic stellate cells (HSCs) and excessive deposition of extracellular matrix (ECM). Research suggests that microRNAs (miRNAs) are a new type of regulator of liver fibrosis. In the present study, we investigated the role of microRNA-9 (miR-9) in the process of liver fibrosis, as well as the underlying mechanism of action. Downregulated levels of miR-9 were found in fibrotic liver tissues and activated HSCs as detected by qRT-PCR; whereas, expression of multidrug resistance-associated protein 1 (MRP1/ABCC1) was upregulated in the fibrotic liver tissues and activated HSCs. CCK-8 and BrdU assays revealed that miR-9 reduced the proliferative ability of the HSCs. In addition, expression levels of ECM-related genes (α-SMA, Col-1 and Timp-1), which are markers of HSC activation, were downregulated by miR-9. Conversely, an miR-9 inhibitor promoted cell proliferation and HSC activation. In addition, a luciferase reporter assay indicated that miR-9 targets the 3-untranslated region (3′-UTR) of MRP1 and causes a significant decrease in MRP1. miR-9 inhibited the activation of the Hedgehog (Hh) pathway and the expression of MRP1, while this suppression was rescued by the overexpression of MRP1. Finally, a CCl4-induced mouse model of liver fibrosis was used to investigate the effects of miR-9 on liver fibrosis in vivo. The results showed that miR-9 abrogated hepatic fibrosis by suppressing the expression of MRP1 in CCl4-induced liver fibrotic mice. In conclusion, the present study demonstrated that miR-9 suppresses the proliferation and activation of HSCs through the Hh pathway by targeting MRP1, which suggests that miR-9 has therapeutic potential for liver fibrosis.

Dynamic vision processing at the edge requires in-sensor spiking neural networks (SNNs) to achieve high energy efficiency and rapid processing. Although optoelectronic leaky integrate-and-fire (LIF) neurons are essential for optical sensing and sparse coding, their practical utility has been hindered by incomplete emulation of biological behaviors and integration difficulties with synaptic devices. Here, we show an optoelectronic LIF neuron based on a MoS 2 phototransistor that reproduces key neuronal features, including multispectral sensing, capacitor-less integration, and threshold-triggered spiking. This neuron supports complementary rate and time-to-first-spike coding, enabling versatile visual information processing at the hardware level. Furthermore, we achieve the homogeneous integration of these neurons with MoS 2 ferroelectric synapses on a single substrate, unifying volatile optical encoding with non-volatile weight storage. The integrated SNN system attains recognition accuracies of 91.7% for color recognition and 93.5% for object detection, indicating its potential for scalable, high-performance next-generation neuromorphic vision systems. Integrating volatile optical sensing with non-volatile memory is crucial for neuromorphic vision applications. Wang et al. propose a homogeneous integration scheme that combines optoelectronic neurons and ferroelectric synapses on a single substrate for color recognition and object detection tasks.

Following the publication of this article, a concerned reader drew to our attention that in Fig. 5C on p. 1704, showing histological images of mouse livers stained with H&E, unexpected areas of similarity were identified in terms of the staining patterns revealed within the data panels themselves. After having conducted an internal investigation, the Editor of Oncology Reports has reached the conclusion that the overlapping portions of data shown in this figure were unlikely to have arisen by coincidence. Therefore, on the grounds of a lack of confidence in the integrity of these data, the Editor has decided that the article should be retracted from the publication. The authors were asked for an explanation to account for these concerns, but the Editorial Office did not receive any reply. The Editor apologizes to the readership for any inconvenience caused, and thanks the interested reader for drawing this matter to our attention. [Oncology Reports 37: 1698‑1706, 2017; DOI: 10.3892/or.2017.5382].Following the publication of this article, a concerned reader drew to our attention that in Fig. 5C on p. 1704, showing histological images of mouse livers stained with H&E, unexpected areas of similarity were identified in terms of the staining patterns revealed within the data panels themselves. After having conducted an internal investigation, the Editor of Oncology Reports has reached the conclusion that the overlapping portions of data shown in this figure were unlikely to have arisen by coincidence. Therefore, on the grounds of a lack of confidence in the integrity of these data, the Editor has decided that the article should be retracted from the publication. The authors were asked for an explanation to account for these concerns, but the Editorial Office did not receive any reply. The Editor apologizes to the readership for any inconvenience caused, and thanks the interested reader for drawing this matter to our attention. [Oncology Reports 37: 1698‑1706, 2017; DOI: 10.3892/or.2017.5382].

Object detection, as a fundamental task in computer vision, mainly performs the classification and localization of objects in images or videos. However, traditional edge computing platforms fall short of meeting the demands for state‐of‐the‐art object detection model size and computing power. Here, a 128 Mb phase change memory chip is fabricated with a high memory yield of 99.99999% in a 40 nm node and utilized for efficient in‐memory vector‐matrix multiplication and in‐memory max computation. In particular, in order to mitigate the significant programming energy overheads for large‐scale memristor arrays and the reliance on high‐precision analog‐to‐digital‐converter (ADC) in compute‐in‐memory operations, a novel mixed‐precision weight mapping strategy is adopted. Compared with traditional schemes, the ADC modules achieve up to a 22.3× reduction in energy consumption while maintaining equivalent network performance. Ultimately, this memristive in‐memory object detection system demonstrates 4,180× higher energy efficiency and 228× greater computational throughput compared to GPU implementations.

Patterning ultrathin MoS2 layers with regular edges or controllable shapes is appealing since the properties of MoS2 sheets are sensitive to the edge structures. In this work, we have introduced a simple, effective and well-controlled technique to etch layered MoS2 sheets with well-oriented equilateral triangular pits by simply heating the samples in air. The anisotropic oxidative etching is greatly affected by the surrounding temperature and the number of MoS2 layers, whereby the pit sizes increase with the increase of surrounding temperature and the number of MoS2 layers. First-principles computations have been performed to explain the formation mechanism of the triangular pits. This technique offers an alternative avenue to engineering the structure of MoS2 sheets.

Memristive in-memory sorting has been proposed recently to improve hardware sorting efficiency. Using iterative in-memory min computations, data movements between memory and external processing units can be eliminated for improved latency and energy efficiency. However, the bit-traversal algorithm to search the min requires a large number of column reads on memristive memory. In this work, we propose a column-skipping algorithm with help of a near-memory circuit. Redundant column reads can be skipped based on recorded states for improved latency and hardware efficiency. To enhance the scalability, we develop a multi-bank management that enables column-skipping for dataset stored in different memristive memory banks. Prototype column-skipping sorters are implemented with a 1T1R memristive memory in 40nm CMOS technology. Experimented on a variety of sorting datasets, the length-1024 32-bit column-skipping sorter with state recording of 2 demonstrates up to 4.08x speedup, 3.14x area efficiency and 3.39x energy efficiency, respectively, over the latest memristive in-memory sorting.

Sorting is fundamental and ubiquitous in modern computing systems. Hardware sorting systems are built based on comparison operations with Von Neumann architecture, but their performance are limited by the bandwidth between memory and comparison units and the performance of complementary metal-oxide-semiconductor (CMOS) based circuitry. Sort-in-memory (SIM) based on emerging memristors is desired but not yet available due to comparison operations that are challenging to be implemented within memristive memory. Here we report fast and reconfigurable SIM system enabled by digit read (DR) on 1-transistor-1-resistor (1T1R) memristor arrays. We develop DR tree node skipping (TNS) that support variable data quantity and data types, and extend TNS with multi-bank, bit-slice and multi-level strategies to enable cross-array TNS (CA-TNS) for practical adoptions. Experimented on benchmark sorting datasets, our memristor-enabled SIM system presents up to 3.32x~7.70x speedup, 6.23x~183.5x energy efficiency improvement and 2.23x~7.43x area reduction compared with state-of-the-art sorting systems. We apply such SIM system for shortest path search with Dijkstra's algorithm and neural network inference with in-situ pruning, demonstrating the capability in solving practical sorting tasks and the compatibility in integrating with other compute-in-memory (CIM) schemes. The comparison-free TNS/CA-TNS SIM enabled by memristors pushes sorting into a new paradigm of sort-in-memory for next-generation sorting systems.