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The Zero Degree Calorimeters (ZDC) of the ALICE experiment at the LHC were designed to characterize the event and monitor the luminosity in heavy-ion collisions. In order to fully exploit the potential offered by the LHC increased luminosity in Run 3, while preserving the time and charge resolution performance, the ZDC readout system was upgraded to allow the acquisition of all collisions in self-triggered mode without dead time. The presence of electromagnetic dissociation (EMD) processes makes the ZDC operating conditions extremely challenging, raising the readout rate for the channels of the most exposed calorimeters up to 1.4 Mevents/s, compared to an hadronic rate of about 50 Kevents/s sustained by all other detectors. The new acquisition chain is based on a commercial 12 bit digitizer with a sampling rate of 1 GSps, assembled on an FPGA Mezzanine Card. The signals produced by the ZDC channels are digitized, the samples are processed through an FPGA that, thanks to a custom trigger algorithm, flags for readout the relevant portion of the waveform and extracts information such as timing, baseline average and event rate. The system is fully integrated with the ALICE data taking infrastructure and acquired physics data during the 2023 LHC heavy-ion data taking. The architecture of the new readout system, the auto trigger strategy, and the ZDC performance during the 2023 Pb–Pb collisions are presented.

The Zero Degree Calorimeter (ZDC) was designed to provide the event geometry and luminosity measurements in heavy-ion operation. In order to exploit the potential offered by the LHC’s increased luminosity in Run 3, the ZDC upgraded its readout system to acquire all collisions in self triggered mode without dead time. The purpose of the upgrade was to enable the detector to cope with the increased event rate while preserving its time and charge resolution performance. The ZDC operating conditions in Run 3 Pb – Pb collisions are extremely challenging due to the presence of electromagnetic dissociation processes (EMD). For example when running in self-triggered mode the ZDC system will need to sustain a readout rate of ∼2.5 MHz for the channels of the most exposed calorimeters compared to the foreseen hadronic rate of 50 kHz sustained by the other detectors. The previous electronics, based on Charge-to-digital converters (QDCs), with a fixed dead time of ∼ 10 μμs, and on readout through VME bus, could not cope with such a high rate. Moreover, a crucial aspect of the ZDC operation in Run 3 is acquiring the events with a reduced bunch spacing of 50 ns (lower than the length of the signal of ∼ 60 ns) in the presence of high signal dynamics (from a single neutron to ∼ 60 neutrons). The new acquisition chain is based on a 12 bit digitizer with a sampling rate of about 1 GS/s, assembled on an FPGA Mezzanine Card. The signals produced by the ZDC channels are digitized, and samples are processed through an FPGA to extract information such as timing, baseline average estimation and luminosity. The architecture of the new readout system, the auto trigger strategy, the firmware organization and the ZDC performance during 2022 Pb–Pb collisions are presented.

This work presents the development of a 64-channel application-specific integrated circuit (ASIC), implemented to detect the optical Cherenkov light from sub-orbital and orbital altitudes. These kinds of signals are generated by ultra-high energy cosmic rays (UHECRs) and cosmic neutrinos (CNs). The purpose of this front-end electronics is to provide a readout unit for a matrix of silicon photo-multipliers (SiPMs) to identify extensive air showers (EASs). Each event can be stored into a configurable array of 256 cells where the on-board digitization can take place with a programmable 12-bits Wilkinson analog-to-digital converter (ADC). The sampling, the conversion process, and the main digital logic of the ASIC run at 200 MHz, while the readout is managed by dedicated serializers operating at 400 MHz in double data rate (DDR). The chip is designed in a commercial 65 nm CMOS technology, ensuring a high configurability by selecting the partition of the channels, the resolution in the interval 8–12 bits, and the source of its trigger. The production and testing of the ASIC is planned for the forthcoming months.