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The Medium Energy X-ray telescope (ME) is one of the three main telescopes on board the Insight hard X-ray modulation telescope ( Insight- HXMT) astronomy satellite. ME contains 1728 pixels of Si-PIN detectors sensitive in 5–30 keV with a total geometrical area of 952 cm 2 . The application specific integrated circuit (ASIC) chip, VA32TA6, is used to achieve low power consumption and low readout noise. The collimators define three kinds of field of views (FOVs) for the telescope, 1°×4°, 4°×4°, and blocked ones. Combination of such FOVs can be used to estimate the in-orbit X-ray and particle background components. The energy resolution of ME is ~3 keV at 17.8 keV (FWHM) and the time resolution is 255 μs. In this paper, we introduce the design and performance of ME.

The purpose of this study was to investigate the feasibility of a time-of-flight (TOF) brain positron emission tomography (PET) providing high-quality images. It consisted of 30 detector blocks arranged in a ring with a diameter of 257 mm and an axial field of view of 52.2 mm. Each detector block was composed of two detector modules and two application-specific integrated circuit (ASIC) chips. The detector module was composed of an 8 × 8 array of 3 × 3 mm2 multi-pixel photon counters and an 8 × 8 array of 3.11 × 3.11 × 15 mm3 lutetium yttrium oxyorthosilicate scintillators. The 64-channel individual readout ASIC was used to acquire the position, energy, and time information of a detected gamma ray. A coincidence timing resolution of 187 ps full width at half maximum (FWHM) was achieved using a pair of channels of two detector modules. The energy resolution and spatial resolution were 6.6 ± 0.6% FWHM (without energy nonlinearity correction) and 2.5 mm FWHM, respectively. The results of this study demonstrate that the developed TOF brain PET could provide excellent performance, allowing for a reduction in radiation dose or scanning time for brain imaging due to improved sensitivity and signal-to-noise ratio.

This paper focuses on the hardware aspects of battery management systems (BMS) for electric vehicle and stationary applications. The purpose is giving an overview on existing concepts in state-of-the-art systems and enabling the reader to estimate what has to be considered when designing a BMS for a given application. After a short analysis of general requirements, several possible topologies for battery packs and their consequences for the BMS’ complexity are examined. Four battery packs that were taken from commercially available electric vehicles are shown as examples. Later, implementation aspects regarding measurement of needed physical variables (voltage, current, temperature, etc.) are discussed, as well as balancing issues and strategies. Finally, safety considerations and reliability aspects are investigated.

Modern networks used for integrating custom Internet of Things (IoT) systems and devices have restrictions and requirements unique to their individual applications. These application specific demands require custom designed hardware to maximize throughput, security and data integrity whilst minimizing latency, power consumption, and form factor. Within this paper, we describe current, state-of-the-art works that utilize FPGAs for IoT network developments. We analyze two categories of works: those that prioritize reducing power consumption, and those that prioritize networking features. Further, we describe how future works can improve upon these designs and therefore improve the efficiency of resource-constrained IoT networks.

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pArms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm2, and the power consumption of the current sensing system is 12 mW.

Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

Acid-sensing ion channels (ASICs) are proton-gated ion channels broadly expressed in the vertebrate nervous system, converting decreased extracellular pH into excitatory sodium current. ASICs were previously thought to be a vertebrate-specific branch of the DEG/ENaC family, a broadly conserved but functionally diverse family of channels. Here, we provide phylogenetic and experimental evidence that ASICs are conserved throughout deuterostome animals, showing that ASICs evolved over 600 million years ago. We also provide evidence of ASIC expression in the central nervous system of the tunicate, Oikopleura dioica. Furthermore, by comparing broadly related ASICs, we identify key molecular determinants of proton sensitivity and establish that proton sensitivity of the ASIC4 isoform was lost in the mammalian lineage. Taken together, these results suggest that contributions of ASICs to neuronal function may also be conserved broadly in numerous animal phyla.

Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson’s disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closed-loop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm 2 silicon area and the average power consumption is 142 μW. The proposed solution achieves a significant reduction in both false alarm rates and power consumption when benchmarked against state-of-the-art counterparts.