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Before Palm Pilots and iPods, PCs and laptops, the term \"computer\" referred to the people who did scientific calculations by hand. These workers were neither calculating geniuses nor idiot savants but knowledgeable people who, in other circumstances, might have become scientists in their own right. When Computers Were Human represents the first in-depth account of this little-known, 200-year epoch in the history of science and technology. Beginning with the story of his own grandmother, who was trained as a human computer, David Alan Grier provides a poignant introduction to the wider world of women and men who did the hard computational labor of science. His grandmother's casual remark, \"I wish I'd used my calculus,\" hinted at a career deferred and an education forgotten, a secret life unappreciated; like many highly educated women of her generation, she studied to become a human computer because nothing else would offer her a place in the scientific world. The book begins with the return of Halley's comet in 1758 and the effort of three French astronomers to compute its orbit. It ends four cycles later, with a UNIVAC electronic computer projecting the 1986 orbit. In between, Grier tells us about the surveyors of the French Revolution, describes the calculating machines of Charles Babbage, and guides the reader through the Great Depression to marvel at the giant computing room of the Works Progress Administration. When Computers Were Human is the sad but lyrical story of workers who gladly did the hard labor of research calculation in the hope that they might be part of the scientific community. In the end, they were rewarded by a new electronic machine that took the place and the name of those who were, once, the computers.

It is demonstrated that neuromorphic materials designed for computational tasks can be effectively implemented by drawing an analogy with trigger-based systems built upon classical binary elements. Among the most promising approaches in this context are systems that perform computations based on the Residue Number System (RNS). A specific implementation of a trigger-based adder employing the proposed methodology is presented and tested through simulation modeling. This adder utilizes the representation of natural numbers as elements of a subtraction ring modulo P, where P is the product of Mersenne prime numbers. This configuration enables component-wise, independent execution of arithmetic operations. It is further shown that analogous trigger-based systems can be realized using recurrent neural network analogs, particularly those implemented with neuromorphic materials. The study emphasizes that it is possible to construct a neural network, especially one based on neuromorphic substrates, that can perform logical operations equivalent to those executed by conventional binary circuitry. A key challenge in the proposed approach lies in implementing an operation analogous to the carry mechanism employed in classical binary adders. An algorithm addressing this issue is proposed, based on the transition from computations modulo P to computations modulo 2P.

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies.

This paper presents a novel Sparse Kogge-Stone adder architecture with a sparsity factor of 2, offering a compelling solution to the challenges faced by parallel prefix adders. The superior performance is achieved by including the hybrid carry prefix generator adder (HCPGA), which leads to the elimination of redundant components, and improvements in power consumption and circuit area without compromising computation speed. The proposed hybrid architecture efficiently generates carry prefixes that negates the need for the conventional generate and propagate block, resulting in reduced computational complexity. The effectiveness of the proposed architecture has been extensively validated using Cadence Virtuoso in the 45nm technology node. In addition to evaluating standard performance parameters such as power, delay, and area, comprehensive Monte Carlo simulations and process corner analyses have been performed to ensure the robustness and reliability of the design. Furthermore, the practical application of the proposed architecture has been demonstrated by integrating it into a digital multiplier architecture, showcasing its potential to enhance the computational capabilities of complex arithmetic circuits. This research contributes to the advancement of efficient adder designs for high-performance computing applications, making it highly beneficial and relevant for modern digital circuit designs.

Analog optical computing (AOC) has attracted great attention over the past few years, because of its ultra-high speed (potential for real-time processing), ultra-low power consumption, and parallel processing capabilities. In this article, we design an adder and an ordinary differential equation solver (ODE) on chip by Fourier optics and metasurface techniques. The device uses the 4f system consisting of two metalenses on both sides and one middle metasurface (MMS) as the basic structure. The MMS that performs the computing is the core of the device and can be designed for different applications, i.e., the adder and ODE solver in this article. For the adder, through the comparison of the two input and output signals, the effect of the addition can be clearly displayed. For the ODE solver, as a proof-of-concept demonstration, a representative optical signal is well integrated into the desired output distribution. The simulation result fits well with the theoretical expectation, and the similarity coefficient is 98.28%. This solution has the potential to realize more complex and high-speed artificial intelligence computing. Meanwhile, based on the direct-binary-search (DBS) algorithm, we design a signal generator that can achieve power splitting with the phase difference of π between the two output waveguides. The signal generator with the insertion loss of −1.43 dB has an ultra-compact footprint of 3.6 μm× 3.6 μm. It can generate a kind of input signal for experimental verification to replace the hundreds of micrometers of signal generator composed of a multi-mode interference (MMI) combination used in the verification of this type of device in the past.

This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking.

Quantum-dot cellular automata (QCA) is the beginning of novel technology and is capable of an appropriate substitute for orthodox semiconductor transistor technology in the nanoscale extent. A competent adder and subtractor circuit can perform a substantial function in devising arithmetic circuits. The future age of digital techniques will exercise QCA as preferred nanotechnology. The QCA computational procedures will be simplified with an effective full adder and subtractor circuit. The deficiencies of variations and assembly still endure as a setback in QCA based outlines, and being capricious and inclined to error is the limitation of these circuits. In this study, a new full adder and subtractor design using unique 3-input XOR gate with cells redundancy is proposed. This designs can be utilized to form different expedient QCA layouts. The structures are formed in a single layer deprived of cross-wiring. Besides, this study is directed to the analysis of the functionality and energy depletion possessions of the outlined full adder and subtractor circuits. For the first time, QCADesigner-Energy (QD-E) version 2.0.3 tool is utilized to find the overall depleted energy. The attained effects with QCADesigner have verified that the outlined design has enhanced functioning in terms of intricacy, extent, and latency in contrast to the earlier designs. Moreover, the redundant form of full adder and subtractor has uncomplicated and robust arrangement competing typical styles.

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.