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Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits’ schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits’ schematics, which consists of converting the circuit’s related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit’s schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit’s classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits’ structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.

Neurons can exhibit abundant electrical activities due to physical effects of various electrophysiology environments. The electromagnetic induction flows can be triggered by changes in neuron membrane potential, which can be equivalent to a memristor applying on membrane potential. To imitate the electromagnetic induction effects, we propose a three-variable memristor-based Wilson neuron model. Using several kinetic analysis methods, the memristor parameter- and initial condition-related electrical activities are explored intensively. It is revealed that the memristive Wilson neuron model can display rich electrical activities, including the asymmetric coexisting electrical activities and antimonotonicity phenomenon. Finally, using off-the-shelf discrete components, an analog circuit on a hardware level is implemented to verify the numerically simulated coexisting electrical activities. Studying these rich electrical activities in neurons can build the groundwork to widen the neuron-based engineering applications.

This paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12‐bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9‐μV input referred noise (IRN), 10.8‐effective number of bits (ENOB), 37.8‐μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18‐μm CMOS process and validated by in‐vivo experiment on a lab mouse with a 36‐channel silicon‐based neural probe. A 36‐channel neural recording ASIC is designed and implemented in this letter. The proposed ASIC uses modular digital pixel (MDP) technique to improve the expandability and robustness by eliminating long routing of sensitive analog signals on chip and can be easily expanded to high‐channel‐count application without re‐design of analog circuit.

In this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier. The proposed comparator is post‐layout simulated within a standard 180‐nm CMOS technology. In the worst‐case scenario, the energy efficiency and the delay of the comparator are improved by more than 80% compared to the conventional single‐stage comparator. A rail‐to‐rail regenerative comparator with inverse inverter pre‐amplifier for low supply voltage applications.

With the rapid development of advanced technologies in the Internet of Things era, higher requirements are needed for next‐generation electronic devices. Fortunately, organic thin film transistors (OTFTs) provide an effective solution for electronic skin and flexible wearable devices due to their intrinsic features of mechanical flexibility, lightweight, simple fabrication process, and good biocompatibility. So far considerable efforts have been devoted to this research field. This article reviews recent advances in various promising and state‐of‐the‐art OTFTs as well as related integrated circuits with the main focuses on: (I) material categories of high‐mobility organic semiconductors for both individual transistors and integrated circuits; (II) effective device architectures and processing techniques for large‐area fabrication; (III) important performance metrics of organic integrated circuits and realization of digital and analog devices for future smart life; (IV) applicable analytical models and design flow to accelerate the circuit design. In addition, the emerging challenges of OTFT‐based integrated circuits, such as transistor uniformity and stability are also discussed, and the possible methods to solve these problems at both transistor and circuit levels are summarized. Organic thin film transistors (OTFTs) hold great potential for future smart life due to their intrinsic features of mechanical flexibility, lightweight, simple fabrication process, and good biocompatibility. This article reviews recent advances in various promising and state‐of‐the‐art OTFTs as well as related integrated circuits with the main focus on high‐performance material categories, device architectures and processing techniques, digital and analog devices, and analytical models and design flow. Additionally, the emerging challenges of OTFT‐based integrated circuits and possible solutions are also discussed.

Catalytically dead Cas9 (dCas9) is a programmable transcription factor that can be targeted to promoters through the design of small guide RNAs (sgRNAs), where it can function as an activator or repressor. Natural promoters use overlapping binding sites as a mechanism for signal integration, where the binding of one can block, displace, or augment the activity of the other. Here, we implemented this strategy in Escherichia coli using pairs of sgRNAs designed to repress and then derepress transcription through competitive binding. When designed to target a promoter, this led to 27‐fold repression and complete derepression. This system was also capable of ratiometric input comparison over two orders of magnitude. Additionally, we used this mechanism for promoter sequence‐independent control by adopting it for elongation control, achieving 8‐fold repression and 4‐fold derepression. This work demonstrates a new genetic control mechanism that could be used to build analog circuit or implement cis‐regulatory logic on CRISPRi‐targeted native genes. Synopsis A regulatory control mechanism is developed based on the competitive binding of dCas9 to DNA by two guide RNAs. One represses a target gene (CRISPRi) and the second displaces the repressing dCas9 without interfering with the gene’s transcription. Complete derepression is achieved against CRISPRi targeted to a promoter. Derepression is less efficient when CRISPRi blocks transcriptional elongation within a gene. Synthetic cis‐regulatory logic can be built using competing sgRNAs, without having to add operators to the promoter. This mechanism is used to build a ratiometric control circuit that responds to the ratio of the activities of two input promoters. Graphical Abstract A regulatory control mechanism is developed based on the competitive binding of dCas9 to DNA by two guide RNAs. One represses a target gene (CRISPRi) and the second displaces the repressing dCas9 without interfering with the gene’s transcription.

The presence of RF components in mixed-signal circuits make it a challenging task to resolve tradeoffs among performance specifications. In order to ease the process of circuit design, these tradeoffs are being analyzed using multi-objective optimization methodologies. This paper presents a hybrid multi-objective optimization framework (MHPSO), a combination of particle swarm optimization and simulated annealing. The framework emphasizes on preserving nondominated solutions in an external archive. The multi-dimensional space excluding the archive is divided into several sub-spaces according to a velocity-temperature mapping scheme. Further, the solutions in each sub-space are optimized using simulated annealing for generation of a Pareto front. The framework is extended by incorporating crowding distance comparison operator (MHPSO-CD) to maintain nondominated solutions in the archive. The effectiveness of proposed methodologies is demonstrated for performance space exploration of three electronic circuits, i.e., a two-stage operational amplifier, a folded cascode operational amplifier, and a low noise amplifier with inductive source degeneration. Additionally, the performance of proposed algorithms (MHPSO, MHPSO-CD) are evaluated on various test functions, and the results are compared with standard multi-objective evolutionary algorithms.

Correct diagnosing analog circuit fault is beneficial to the circuit’s health management, and its core challenge is extracting essential features from the circuit’s output signals. Wavelet transform is a classical features extraction method whose performance relies on its wavelet basis function deeply. However, there are no satisfying rules to discover an optimal wavelet basis function for wavelet transform. In this paper, an improved wavelet transform with optimal wavelet basis function selection strategy is proposed. In the strategy, the optimal wavelet basis function is selected based on calculating the distance score and mean score of its features, and the features extracted by the optimal wavelet basis function are considered as the best features of signals. Subsequently, the features are split into training data and testing data randomly and evenly. By using the training data, a multiple kernel extreme learning machine (MKELM) based diagnosing model is initialized, and the parameters of MKELM are yielded by using particle swarm optimization algorithm. Finally, the MKELM is used to identify the faults of testing data for the purpose of verifying its performance. Fault diagnosis experiments of three circuits are performed to show the proposed optimal wavelet basis function selection strategy and MKELM’s establishing process. Comparison experiments are performed to verify that the optimal wavelet basis function selection strategy is effective and MKELM is better than other classifiers in analog circuit fault diagnosis.

In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint.

This work proposes an optimized support vector model and a variable ranking-based test node selection approach for identifying parametric faults in analog circuits using a fault dictionary. Test node selection is essential for fault dictionary-based fault detection to reduce the dimensionality and test process complexity. To determine an appropriate set of test nodes, a feature selection technique based on variable ranking is used, as it is computationally efficient and involves sorting and score estimation. In the proposed method, test nodes are ranked using a score function based on data variability, where the nodes with the highest data variability are assigned the highest rank. This ranking ensures that the most informative test nodes are prioritized for fault detection. An optimized support vector model is used for fault diagnosis to improve classification accuracy. The results show the effectiveness of this approach. The performance of the proposed method is validated by measuring the fault detection accuracy on benchmark circuits.