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This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage. This letter presents an 11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The proposed calibration technique reduces the comparator offset mismatch to within 0.25 LSB at 11 b resolution, enabling the implementation of high‐resolution 2b/cycle SAR ADC.

This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies the length of each resistor in the resistor loop via a merging operation and reduces the number of switches and resistors. In addition, the effect of switches is mitigated using the proposed switch effect reduction method. The accuracy of the proposed BIST is demonstrated by the reduction in the switch effect. The experimental results show that the proposed BIST reduces resource usages and the mismatch error caused by the switches.

Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range. The authors present a hardware prototype of a high‐dynamic range analog‐to‐digital converter (ADC) where a folding operation enhances the dynamic range. The authors show sampling and perfect reconstruction of different classes of signals whose dynamic ranges are larger than that of ADC's dynamic range.

ABSTRACT Pipelined analogue‐to‐digital converters suffer from inter‐stage gain errors and inter‐stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial‐based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants.

In this study, a digital calibration method applicable for a continuous‐time sigma‐delta analogue‐to‐digital converter is proposed using the AC injection technique. The proposed technique directly calibrates the integration accuracy of a converter instead of only trimming the capacitors. Compared with the existing calibration methods, the proposed method does not require complex timing logic processing or additional capacitors and does not adversely impact the dynamic performance of the converter. Furthermore, it ensures the accuracy of the converter, regardless of the non‐ideal effects of advanced processes.

With the rapid development and progress of information technology and the wide usage of audio signal processing in underwater acoustic signal processing, acoustic audio signal acquisition, conversion, and transmission technology always play an important role. To enhance the ability of signal acquisition and conversion with high reliability, this paper designs an embedded multi-channel audio conversion module. The module achieves multi-channel, multi-sample rates with synchronous analog-to-digital/digital-to-analog conversion (ADC/DAC) function, and additionally equips with dual network redundancy. The module uses a chip integrated with ARM and programmable logic FPGA as the main control chip. The writing of the underlying driver and application code ensures the reliable operation of the DAC chip and ADC chip and the steady of the network transmission. Through experimental verification, the audio conversion module performs well in multi-channel and multi-sample rates with synchronous ADC/DAC, and the crosstalk between channels is less than -50 dB. The dual network redundancy design and the application of the RS232 serial port ensure the high fidelity, reliability, and reprogramming of the audio conversion function, which shows the design can be used in a wide range of scenarios.

The aim of the article is to examine the issue of eliminating quantization noise in the process of analogue-to-digital conversion by means of timing pulse code modulation. According to the results of the method proposed, it has established that the use of timing modulation significantly increases the number of sampling levels at a given interval without reducing the duration of individual code pulses, that, in its turn, significantly improves signal quality (readability) after the digital-to-analogue conversion on the receiving side.

The tasks of creation and development of cyber-physical systems are considered. Cybernetic and physical subsystems can be presented in digital and analog form. The physical subsystem that simulates nature is presented in an analog form. Physical subsystems and processes, both natural, in particular, and technogenic, can behave like “things in themselves.” Therefore, the processes of synchronization of analog processes with cybernetics are often difficult to formalize or are not performed correctly enough. This applies to both obvious cases in problem areas of ecology, mining, energy, and in computers under conditions of inappropriate behavior of programs, ensuring the reliability of testing. This leads to the emergence of uncertainties accompanying the integration of subsystems and control in the system as a whole. The nature of analog-to-digital and digital-to-analog conversion in the known representation requires taking into account the features at the level of this class of systems. These problems are considered at the levels of deterministic, stochastic and uncertainty. The well-known models of monitoring, control of a physical subsystem cannot be directly used for control. The development of correct control actions is considered from the standpoint of transforming such models. These models for dynamical systems are represented by differential equations. It is necessary to develop input-output models for the subsequent synthesis of controls.

A control-bounded analog-to-digital converter consists of a linear analog system that is subject to digital control, and a digital filter that estimates the analog input signal from the digital control signals. Such converters have many commonalities with delta–sigma converters, but they can use more general analog filters. The paper describes the operating principle, gives a transfer function analysis, and describes the digital filtering. In addition, the paper discusses two examples of such architectures. The first example is a cascade structure reminiscent of, but simpler than, a high-order MASH converter. The second example combines two attractive properties that have so far been considered incompatible. Its nominal conversion noise (assuming ideal components) essentially equals that of the first example. However, its analog filter is a fully connected network to which the input signal is fed in parallel, which potentially makes it more robust against nonidealities.