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A report is presented on the hardware implementation of a parallel multi-channel sampler in 0.5 mu m CMOS technology. The system consists of eight parallel analogue processing channels, each one capable of modulation by a programmable binary chipping sequence. System operation is demonstrated in both Nyquist and compressive sampling of test signals.

Metastability in successive‐approximation register analogue‐to‐digital converters (ADCs) degrades the ADC's signal‐to‐noise and distortion ratio and causes error propagation through the digital equalizers of ADC‐based receivers. To mitigate these issues, a charge‐pump‐based successive‐approximation register metastability calibration method is proposed. This approach operates independently of a fixed voltage or time reference. The calibration process is executed in the background with pipelining, requiring minimal additional power. Comprehensive testing shows that the proposed calibration consistently enhances ADC SNDR and reduces the code error rate across a wide range of sampling rates. A metastable‐bit detection method that utilizes the comparator's resolution time is proposed. Charge pumps convert the resolving time into a voltage, allowing identification of the metastable bit.

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage. This letter presents an 11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The proposed calibration technique reduces the comparator offset mismatch to within 0.25 LSB at 11 b resolution, enabling the implementation of high‐resolution 2b/cycle SAR ADC.

A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals. The proposed VTC is designed in the 28 nm CMOS process, occupying an area of 972 μm2 $\\mu{\\rm m}^2$ . Post‐layout simulation results demonstrate that, with an input voltage of 1.4 Vpp,diff ${\\rm V}_{\\text{pp}, \\text{diff}}$ , the VTC achieves a total harmonic distortion (THD) of −62.9 dB and a spurious‐free dynamic range (SFDR) of 65.5 dB for Nyquist input, while consuming only 1.92 mW of power. A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals.

We introduce an analogue in hyperkaehler geometry of the symplectic implosion, in the case of actions. Our space is a stratified hyperkaehler space which can be defined in terms of quiver diagrams. It also has a description as a non-reductive geometric invariant theory quotient.

A twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications. A twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications.

This paper is devoted to the study of the existence and uniqueness of solutions for n th order differential equations with nonlocal integral boundary conditions. Our results are based on a variety of fixed point theorems. Some illustrative examples are discussed. We also discuss the Caputo type fractional analogue of the higher-order problem of ordinary differential equations.

This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases. This paper introduces a simple and effective Self‐Timed Track‐and‐Hold (STH) method that increases the timing margin for the conversion period without requiring a high‐speed input clock. When comparing the proposed STH method to the traditional Fixed‐Time Track‐and‐Hold (FTH) approach, the STH method consistently yields superior ENOB performance across a longer range of conversion periods.

This paper proposes a novel bandgap voltage reference (BGR) with low temperature coefficient, ultra‐low noise and without start‐up circuit. Designed in a TSMC 180‐nm CMOS technology, this bandgap voltage reference operates in the temperature range of −55 to 125°C with 5‐V voltage supply and provides a 1.2‐V output voltage VBG. A 16.8 ppm/°C temperature coefficient (TC) and the output RMS noise from 0.1 to 10 Hz of 1.69 µV is achieved. The circuit‐level simulation results verify the presented structure. By the improved architecture of the IPTAT generation stage, the proposed BGR can be powered on normally without designing additional start‐up circuit to eliminate equilibrium point, which greatly simplifies the circuit complexity. This paper proposes an ultra‐low noise bandgap voltage reference without start‐up circuit.

The capacitance mismatch problem limits the accuracy improvement of high‐precision SAR ADCs (Successive Approximation Register Analog‐to‐Digital Converters). To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time‐to‐Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13‐bit SAR ADC can be completely eliminated, and the effective number of bits (ENOB) approach the ideal value of 13.18 bits. Additionally, the analog component of this scheme utilizes four inverter chains, two D flip‐flops, and four counters, without requiring a large area for auxiliary calibration capacitors. This article proposes a novel capacitance mismatch calibration method that can effectively improve the accuracy of SAR ADCs. Compared to the previous LMS algorithm or auxiliary capacitor methods, this method uses only a minimal amount of analog hardware, making it suitable for on‐chip integration.