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The article describes the implementation of IoT technology in the teaching of microprocessor technology. The method presented in the article combines the reality and virtualization of the microprocessor technology laboratory. A created IoT monitoring device monitors the students’ microcontroller pins and sends the data to the server to which the teacher is connected via the control application. The teacher has the opportunity to monitor the development of tasks and student code of the program, where the functionality of these tasks can be verified. Thanks to the IoT remote laboratory implementation, students’ tasks during the lesson were improved. As many as 53% (n = 8) of those students who could improve their results achieved an improvement of one or up to two tasks during class. Before the IoT remote laboratory application, up to 30% (n = 6) of students could not solve any task and only 25% (n = 5) solved two tasks (full number of tasks) during the class. Before implementation, 45% (n = 9) solved one problem. After applying the IoT remote laboratory, these numbers increased significantly and up to 50% (n = 10) of students solved the full number of tasks. In contrast, only 10% (n = 2) of students did not solve any task.

Abstract One-dimensional (1D) chaotic maps play a pivotal role in diverse fields, including control systems, secure communication, and modeling complex systems, enabling to capture and analyze the intricate behaviors of dynamical processes. However, their limited control parameter ranges constrain their effectiveness in security applications such as cryptography and pseudo-random number generation. Addressing these concerns, the paper proposes a universalee -CM chaotification model, based on Euler’s number, to enhance the chaotic control parameter range of one-dimensional maps to infinity. The efficacy of theee -CM model has been assessed for thirteen 1D chaotic maps including, Chebyshev, Logistic, Sine, Cubic, Coupled Sine, Cubic Logistic, Quadratic, Renyi, Simple Quadratic, Sine-Sinh-Sine, Singer, Squared Sine Logistic, and Tent maps. Various tests have been conducted to evaluate the enhancedee -CM maps, such as Lyapunov exponents, bifurcation diagrams, approximate and sample entropies, time sensitivity analysis, 0–1 test, 2D and 3D phase plots, and cobweb plots. The findings indicate thatee -CM-based maps exhibit complex chaotic dynamics characterized by elevated positive Lyapunov exponent values, the lack of periodic windows in the bifurcation plot, and higher sample and approximate entropy values. The 2D and 3D phase trajectory plots demonstrate that the points are evenly distributed across the entire phase space, while the cobweb plots illustrate densely packed irregular rectangular trajectories. The 0–1 test produces linearM-tM - t and Brownian motion resembling chaoticp-qp - q plots, alongside indicator value approaching the ideal value of11 . Additionally, theee -CM-based enhanced 1D maps have been employed in designing a pseudo-random bit generator (PRBG). The PRBG has been evaluated in the MATLAB simulator for operational efficiency, bit-generation speed, and performance, alongside a rigorous assessment of its statistical randomness through the NIST tests. The PRBG has proven to be efficient in resource usage, faster in execution, and high-performing, while also successfully passing NIST tests. The PRBG has also been implemented and analyzed on the leading ARM Cortex-M44 -based LPC43574357 IoT development board to showcase its practical efficiency in RAM and ROM memory usage, execution time, current, energy, and power consumption. The results indicate that the PRBG demonstrates smaller memory usage, significantly reduced execution time, and minimal power and energy consumption. Thus, theee -CM based enhanced maps and PRBG stand out as an excellent choice for use in IoT environments, where security, efficiency, and performance are paramount.

This study explores the application of Artificial Intelligence (AI), specifically Convolutional Neural Networks (CNNs), for detecting rice plant diseases using ARM Cortex-M microprocessors. Given the significant role of rice as a staple food, particularly in Malaysia where the rice self-sufficiency ratio dropped from 65.2% in 2021 to 62.6% in 2022, there is a pressing need for advanced disease detection methods to enhance agricultural productivity and sustainability. The research utilizes two extensive datasets for model training and validation: the first dataset includes 5932 images across four rice disease classes, and the second comprises 10,407 images across ten classes. These datasets facilitate comprehensive disease detection analysis, leveraging MobileNetV2 and FD-MobileNet models optimized for the ARM Cortex-M4 microprocessor. The performance of these models is rigorously evaluated in terms of accuracy and computational efficiency. MobileNetV2, for instance, demonstrates a high accuracy rate of 97.5%, significantly outperforming FD-MobileNet, especially in detecting complex disease patterns such as tungro with a 93% accuracy rate. Despite FD-MobileNet’s lower resource consumption, its accuracy is limited to 90% across varied testing conditions. Resource optimization strategies highlight that even slight adjustments, such as a 0.5% reduction in RAM usage and a 1.14% decrease in flash memory, can result in a notable 9% increase in validation accuracy. This underscores the critical balance between computational resource management and model performance, particularly in resource-constrained settings like those provided by microcontrollers. In summary, the deployment of CNNs on microcontrollers presents a viable solution for real-time, on-site plant disease detection, demonstrating potential improvements in detection accuracy and operational efficiency. This study advances the field of smart agriculture by integrating cutting-edge AI with practical agricultural needs, aiming to address the challenges of food security in vulnerable regions.

Deep neural networks have recently become increasingly used for a wide range of applications, (e.g., image and video processing). The demand for edge inference is growing, especially in the areas of relevance to the Internet-of-Things. Low-cost microcontrollers as edge devices are a promising solution for optimal application systems from several points of view such as: cost, power consumption, latency, or real-time execution. The implementation of these systems has become feasible due to the advanced development of hardware architectures and DSP capabilities, while the cost and power consumption have been maintained at a low level. The aim of the paper is to provide a literature review on the implementation of deep neural networks using ARM Cortex-M core-based low-cost microcontrollers. As an emerging research direction, there are a limited number of publications that address this topic at the moment. Therefore, the research papers that stand out have been analyzed in greater detail, to promote further interest of researchers to bring AI techniques to low power standard ARM Cortex-M microcontrollers. The article addresses a niche research domain. Despite the increasing interest manifested toward both (1) edge AI applications and (2) theoretical contributions in DNN optimization and compression, the number of existing publications dedicated to the current topic is rather limited. Therefore, a comprehensive literature survey using systematic mapping is not possible. The presentation focuses on systems that have shown increased efficiency in resource-constrained applications, as well as the predominant impediments that still hinder their implementation. The reader will take away the following concepts from this paper: (1) an overview of applications, DNN architectures, and results obtained using ARM Cortex-M core-based microcontrollers, (2) an overview of low-cost hardware devices and SW development solutions, and (3) understanding recent trends and opportunities.

The end of Moore’s Law aligned with data privacy concerns is forcing machine learning (ML) to shift from the cloud to the deep edge. In the next-generation ML systems, the inference and part of the training process will perform at the edge, while the cloud stays responsible for major updates. This new computing paradigm, called federated learning (FL), alleviates the cloud and network infrastructure while increasing data privacy. Recent advances empowered the inference pass of quantized artificial neural networks (ANNs) on Arm Cortex-M and RISC-V microcontroller units (MCUs). Nevertheless, the training remains confined to the cloud, imposing the transaction of high volumes of private data over a network and leading to unpredictable delays when ML applications attempt to adapt to adversarial environments. To fill this gap, we make the first attempt to evaluate the feasibility of ANN training in Arm Cortex-M MCUs. From the available optimization algorithms, stochastic gradient descent (SGD) has the best trade-off between accuracy, memory footprint, and latency. However, its original form and the variants available in the literature still do not fit the stringent requirements of Arm Cortex-M MCUs. We propose L-SGD, a lightweight implementation of SGD optimized for maximum speed and minimal memory footprint in this class of MCUs. We developed a floating-point version and another that operates over quantized weights. For a fully-connected ANN trained on the MNIST dataset, L-SGD (float-32) is 4.20× faster than the SGD while requiring only 2.80% of the memory with negligible accuracy loss. Results also show that quantized training is still unfeasible to train an ANN from the scratch but is a lightweight solution to perform minor model fixes and counteract the fairness problem in typical FL systems.

One-dimensional (1D) chaotic maps play a pivotal role in diverse fields, including control systems, secure communication, and modeling complex systems, enabling to capture and analyze the intricate behaviors of dynamical processes. However, their limited control parameter ranges constrain their effectiveness in security applications such as cryptography and pseudo-random number generation. Addressing these concerns, the paper proposes a universal e -CM chaotification model, based on Euler’s number, to enhance the chaotic control parameter range of one-dimensional maps to infinity. The efficacy of the e -CM model has been assessed for thirteen 1D chaotic maps including, Chebyshev, Logistic, Sine, Cubic, Coupled Sine, Cubic Logistic, Quadratic, Renyi, Simple Quadratic, Sine-Sinh-Sine, Singer, Squared Sine Logistic, and Tent maps. Various tests have been conducted to evaluate the enhanced e -CM maps, such as Lyapunov exponents, bifurcation diagrams, approximate and sample entropies, time sensitivity analysis, 0–1 test, 2D and 3D phase plots, and cobweb plots. The findings indicate that e -CM-based maps exhibit complex chaotic dynamics characterized by elevated positive Lyapunov exponent values, the lack of periodic windows in the bifurcation plot, and higher sample and approximate entropy values. The 2D and 3D phase trajectory plots demonstrate that the points are evenly distributed across the entire phase space, while the cobweb plots illustrate densely packed irregular rectangular trajectories. The 0–1 test produces linear M - t and Brownian motion resembling chaotic p - q plots, alongside indicator value approaching the ideal value of 1 . Additionally, the e -CM-based enhanced 1D maps have been employed in designing a pseudo-random bit generator (PRBG). The PRBG has been evaluated in the MATLAB simulator for operational efficiency, bit-generation speed, and performance, alongside a rigorous assessment of its statistical randomness through the NIST tests. The PRBG has proven to be efficient in resource usage, faster in execution, and high-performing, while also successfully passing NIST tests. The PRBG has also been implemented and analyzed on the leading ARM Cortex-M 4 -based LPC 4357 IoT development board to showcase its practical efficiency in RAM and ROM memory usage, execution time, current, energy, and power consumption. The results indicate that the PRBG demonstrates smaller memory usage, significantly reduced execution time, and minimal power and energy consumption. Thus, the e -CM based enhanced maps and PRBG stand out as an excellent choice for use in IoT environments, where security, efficiency, and performance are paramount.

In this article, some practical software optimization methods for implementations of fractional order backward difference, sum, and differintegral operator based on Grünwald–Letnikov definition are presented. These numerical algorithms are of great interest in the context of the evaluation of fractional-order differential equations in embedded systems, due to their more convenient form compared to Caputo and Riemann–Liouville definitions or Laplace transforms, based on the discrete convolution operation. A well-known difficulty relates to the non-locality of the operator, implying continually increasing numbers of processed samples, which may reach the limits of available memory or lead to exceeding the desired computation time. In the study presented here, several promising software optimization techniques were analyzed and tested in the evaluation of the variable fractional-order backward difference and derivative on two different Arm® Cortex®-M architectures. Reductions in computation times of up to 75% and 87% were achieved compared to the initial implementation, depending on the type of Arm® core.

Singular value decomposition (SVD) is a central mathematical tool for several emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems, data analytics, sparse representation of signals. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions and parallel implementations have been proposed to overcome this bottleneck. However, as those solutions require additional hardware resources that are not in general available in embedded systems, optimized algorithms are demanded in this context. The aim of this paper is to present an efficient implementation of the SVD algorithm on ARM Cortex-M. To this end, we proceed to (i) present a comprehensive treatment of the most common algorithms for SVD, providing a fairly complete and deep overview of these algorithms, with a common notation, (ii) implement them on an ARM Cortex-M4F microcontroller, in order to develop a library suitable for embedded systems without an operating system, (iii) find, through a comparative study of the proposed SVD algorithms, the best implementation suitable for a low-resource bare-metal embedded system, (iv) show a practical application to Kalman filtering of an inertial measurement unit (IMU), as an example of how SVD can improve the accuracy of existing algorithms and of its usefulness on a such low-resources system. All these contributions can be used as guidelines for embedded system designers. Regarding the second point, the chosen algorithms have been implemented on ARM Cortex-M4F microcontrollers with very limited hardware resources with respect to more advanced CPUs. Several experiments have been conducted to select which algorithms guarantee the best performance in terms of speed, accuracy and energy consumption.

Hydroponic is the process of growing plants without soil, plant root flooded or moist with nutrient-rich solutions in inert material. Hydroponics has become a reality for greenhouse growers in virtually all climates. Large hydroponic installations exist throughout the world for growing flowers, vegetables and some short period fruit like tomato and cucumber. In soilless culture, we must maintain stable pH and conductivity level of nutrient solution to make plant grow well, large variation of pH of certain time will poisoned plant. This paper describes development complete automation hydroponic system, from maintaining stable nutrient composition (conductivity and pH), grow light, and monitor plant environment such as CO2, temperature and humidity. The heart of our automation is ARM Cortex-M4 from ST Microelectronic running ARM mbed OS, the official Real Time Operating System (RTOS) for ARM Cortex-M microcontroller. Using RTOS gives us flexibility to have multithreaded process. Results show that system capable to control desired concentration level with variation of less than 3%, pH sensor show good accuracy 5.83% from pH value 3.23-10. Growing light intensity measurement show result 105 μmol/m2/s therefore we need turn on the light at least 17 hours/day to fulfil plant light requirement. RTOS give good performance with latency and jitter less than 15 us, system overall show good performance and accuracy for automating hydroponic plant in vegetative phase of growth.

Embedded Systems Engineering has grown in recent years to become an integral part of our daily living as it finds striking applications in various spheres of our lives. These range from Manufacturing, Electronic Health, Telecommunications, Construction and Robotics to numerous other fields. Primarily, Embedded Systems are usually a combination of selected electrical and electronic components functioning together under the direct control of a programmed controller. They serve fundamentally as additional units incorporated within already existing infrastructures with the sole aim of providing dedicated services to the larger infrastructure. Many of the controllers used operate on uniquely designed processor cores, instruction sets, and architecture profiles. This paper seeks to elucidate the application of the ARM Cortext-M3 processor based NXP LPC 1768 Microcontroller unit in the design and development of a Temperature Monitoring and Logging System. The write-up starts off with an overview of the principal ARM processor core families, architecture profiles, instruction sets and subsequently, demonstrates its utilization in the design of a Temperature Monitoring and Logging System. The paper shows how the NXP LPC 1768 Microcontroller Unit successfully serves as the brain of the temperature logger device through its standardized interfacing with a TMP102 temperature sensor using the Inter- Integrated Circuit (I2C) protocol. The Microcontroller is programmed using Embedded C while other unique functionalities of the ARM Cortex-M3 core such as Interrupt Handling and System Tick Timer efficiency are also explored.