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A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

A push–pull low‐dropout regulator based on flipped voltage follower is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The push‐current mode with 1.2‐V input and 1‐V output effectively drives load circuits that are sensitive to supply noise. The pull‐current one with 1.2‐V input and 0.2‐V output effectively drives load circuits that are sensitive to ground noise. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns transient response time over load current (IL) of 10 µA to 20 mA. The presented design achieves a fast transient response and a high‐frequency PSR with a low‐gain fast loop (loop‐I), and enhances the low‐frequency PSR and the line/load regulation with a high‐gain slow loop (loop‐II). Furthermore, the circuit features a load regulation less than 0.09 mV/mA over IL of 10 µA to 20 mA and a line regulation less than 0.01 mV/mV, within a 120‐mV ripple applied to supply/ground. This design consumes a 58‐µA quiescent current (IQ) in both push‐current and pull‐current modes. The low‐dropout regulator works well over the load capacitor (CL) of 0 to 30 pF. A push‐pull low‐dropout regulator (LDO) based on flipped voltage follower (FVF) is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The proposed LDO that is fully different from the existing designs, benefits noise‐sensitive wideband circuits that require a high PSR and a fast transient response. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns response time over load current (IL) of 10 µA to 20 mA

The Ising spin model is an efficient method for solving combinatorial optimization problems (COPs) but faces challenges in conventional Von‐Neumann architectures due to high computational costs, especially with the growing data volume in the IoT era. To address this problem, we proposed low power CMOS stochastic bit based Ising machine to efficiently compute COPs. By adopting compute‐in‐memory (CIM) approach for parallel spin computation, we achieved energy efficient spin computing. Furthermore, we harnessed the inherent randomness of CMOS stochastic bit to prevent Ising computing process from being stuck into local minima, effectively mitigating the power penalty associated with the random number generators (RNGs) in the conventional CMOS based Ising machines. We demonstrated the feasibility of our design by solving NP‐complete graph coloring problem with four vertices and three colors using TSMC 65 nm GP process. Moreover, the proposed CMOS stochastic bit based spin unit consumes the lowest power/spin among the state‐of‐the‐art Ising machine researches, with power/spin of 1.07 μW $\\mu{\\rm W}$and energy/spin of 107 fJ. The Ising spin model efficiently solves combinatorial optimization problems (COPs) but faces challenges in conventional Von‐Neumann architectures due to high computational costs. We proposed a low‐power CMOS stochastic bit‐based Ising machine using a compute‐in‐memory (CIM) approach to achieve energy‐efficient spin computing while mitigating the power penalty from on‐chip RNGs. The design's feasibility was demonstrated by solving a four‐vertex, three‐color NP‐complete graph coloring problem using the TSMC 65nm GP process.

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

Floating-gate transistors are increasingly used for digital and/or analogue non-volatile memory in standard CMOS integrated circuits. The mask design of the floating-gate's tunnelling junction, where erasure and/or writing occur, is examined. Aided by static and transient tunnelling current measurements for a variety of tunnelling junctions, recommendations for constructing these junctions to minimise the duration, power consumption and oxide degradation of programming are presented.

A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 μm CMOS process and occupies 0.15 mm2.

A 1.1 µW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 µm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

A low power single lead electrocardiogram front-end acquisition system in 0.18 μm CMOS operating at 0.5 V is presented here. The analogue blocks in low noise amplifier (LNA), filters and passive elements that perform amplification and DC offset cancellation are replaced by a moving average voltage to time converter (MA-VTC) to get amplification and anti-aliasing in the time domain. A digital feedback algorithm is used to cancel out the DC offset. The front-end structure is designed in the sub-threshold region of MOS to reduce the power consumption in the circuit. The proposed architecture consumes 50 nW of power with a gain of 670 μs/V. The output of the front-end is fed to an all digital time-to-digital converter (TDC) that operates in the near threshold region with a resolution of 586.4 ps and 32.5 μW power consumption.

Hybrid infrared (IR) focal plane arrays consist of an array of IR photo-detectors, bump-bonded to a silicon CMOS readout integrated circuit (ROIC) chip. Design and optimisation of ROIC for quantum dot IR detectors is a multidimensional problem. The major design challenge is to select appropriate readout circuit topology to meet the large dynamic range requirement of quantum dot IR photo-detectors within the area dictated by the matched pixel size. Proposed is an efficient design optimisation for ROIC. The optimisation is based on a proposed decision matrix, which leads to a decision merit for ROIC design. Four main specifications, i.e. charge handling capacity, noise, power dissipation and detector bias voltage variations, have been considered. Various architectures have been compared using circuit design, simulation and implementation. The targeted ROIC specifications for a test chip containing a 4 × 4 array are: 5 Mē charge handling capacity, 30 × 30 µm maximum pixel size, snapshot mode of operation, variable integration time, 5 megapixels/s (Mpps) readout rate and readout noise of 600ē at ambient temperature. Also presented is a design with 5 Mē charge handling capacity, which has not been reported for 180 nm CMOS process earlier.

Reformer reduces redundant self‐attention computations via hash bucketing. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory (ReCIM) accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Additionally, we introduce a reusable weight array which is suitable for matrix operations across various processes of self‐attention, minimising unnecessary area overhead and enhancing device reusability. The proposed 4 Kb ReCIM macro was analysed using 28‐nm CMOS technology. Simulation results demonstrate that the macro achieves a frequency of 500 MHz at a supply voltage of 0.9 V. During the hash bucketing process, energy efficiency reaches 9.74 TOPS/W. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Simulation results show that the data processing frequency for implementing hash bucketing is as high as 500 MHz, and the energy efficiency is 9.74 TOPS/W.