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With the development of technology, systems gravitate towards increasing in their complexity, miniaturization, and level of automation. Amongst these systems, ultrasonic devices have adhered to this trend of advancement. Ultrasonic systems require transducers to generate and sense ultrasonic signals. These transducers heavily impact the system’s performance. Advancements in microelectromechanical systems have led to the development of micromachined ultrasonic transducers (MUTs), which are utilized in miniaturized ultrasound systems. Piezoelectric micromachined ultrasonic transducers (PMUTs) exhibit higher capacitance and lower electrical impedance, which enhances the transducer’s sensitivity by minimizing the effect of parasitic capacitance and facilitating their integration with low-voltage electronics. PMUTs utilize high-yield batch microfabrication with the use of thin piezoelectric films. The deposition of thin piezoelectric material compatible with complementary metal-oxide semiconductors (CMOS) has opened novel avenues for the development of miniaturized compact systems with the same substrate for application and control electronics. PMUTs offer a wide variety of applications, including medical imaging, fingerprint sensing, range-finding, energy harvesting, and intrabody and underwater communication links. This paper reviews the current research and recent advancements on PMUTs and their applications. This paper investigates in detail the important transduction metrics and critical design parameters for high-performance PMUTs. Piezoelectric materials and microfabrication processes utilized to manufacture PMUTs are discussed. Promising PMUT applications and outlook on future advancements are presented.

Lead sulfide (PbS) colloidal quantum dot (CQD) photodiodes integrated with silicon‐based readout integrated circuits (ROICs) offer a promising solution for the next‐generation short‐wave infrared (SWIR) imaging technology. Despite their potential, large‐size CQD photodiodes pose a challenge due to high dark currents resulting from surface states on non‐passivated (100) facets and trap states generated by CQD fusion. In this work, we present a novel approach to address this issue by introducing double‐ended ligands that supplementally passivate (100) facets of halide‐capped large‐size CQDs, leading to suppressed bandtail states and reduced defect concentration. Our results demonstrate that the dark current density is highly suppressed by about an order of magnitude to 9.6 nA cm−2 at −10 mV, which is among the lowest reported for PbS CQD photodiodes. Furthermore, the performance of the photodiodes is exemplary, yielding an external quantum efficiency of 50.8% (which corresponds to a responsivity of 0.532 A W−1) and a specific detectivity of 2.5 × 1012 Jones at 1300 nm. By integrating CQD photodiodes with CMOS ROICs, the CQD imager provides high‐resolution (640 × 512) SWIR imaging for infrared penetration and material discrimination. This work explores the potential of PbS colloidal quantum dots (CQDs) directly integrated with CMOS circuits for high‐resolution short‐wave infrared (SWIR) imaging. By using double‐ended ligands on (100) facets of CQDs, suppression of bandtails and defects is achieved. The prepared CQD photodiodes exhibit excellent performance with low dark current and high responsivity, providing a promising solution for SWIR imaging applications.

This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

On-chip transformers are considered to be the primary components in many RF wireless applications. This paper provides an in-depth review of on-chip transformers, starting with a presentation on the various equivalent circuit models to represent transformer behavior and characterize their performance. Next, a comparative study on the different design and layout strategies is provided, and the fabrication techniques for on-chip implementation of transformers are discussed. The critical performance parameters to characterize on-chip transformers, such as the Q-factor, coupling factor (k), resonance frequency (fSR), and others, are discussed with reference to trade-offs in silicon chip real-estate. The performance parameters and area requirements for different types of on-chip transformers are summarized in tabular form and compared. Several techniques for performance enhancement of on-chip transformers, including the different types of micromachining and integration approaches stemming from MEMS (microelectromechanical systems) technologies are also analyzed. Lastly, the different uses and applications of on-chip transformers are discussed to highlight the evolution of on-chip transformer technology over the recent years and provide directions for future work in this field.

The current state of affairs requires a highly sensitive, accurate, fast, and power-efficient biosensor. The proposed work investigates the performance of a Germanium-based dielectric-modulated junctionless charge plasma tunnel field-effect transistor (Ge-DMJ-CPTFET) as a label-free biosensor. The nanogap cavity is formed by removing gate oxide material from underneath the source electrode. The target biomolecules are modeled inside the nanogap cavity. The biomolecules are identified using their hereditary properties, such as charge density and dielectric constant. The Dielectric Modulation technique and Charge-Plasma concept have been used to investigate the biomolecules immobilized in the nanogap cavity. Germanium exhibits high carrier mobility and superior tunneling characteristics compared to silicon, allowing for improved charge transport across the device channels. The low energy-band gap of Ge helps to reduce tunneling width and increase drain current. The performance of the proposed device is investigated in terms of band energy, electric field, and electric potential at different values of dielectric constant and charge densities of the biomolecules. Moreover, the Sensitivity of the proposed device is investigated for both neutral and charged biomolecules. Along with a label-free biosensor, Ge-DMJ-CPTFET is free from random dopant variations, low thermal budget, and is compatibility with silicon technology.

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined.

Covering a whole surface of a robot with tiny sensors which can measure local pressure and transmit the data through a network is an ideal solution to give an artificial skin to robots to improve a capability of action and safety. The crucial technological barrier is to package force sensor and communication function in a small volume. In this paper, we propose the novel device structure based on a wafer bonding technology to integrate and package capacitive force sensor using silicon diaphragm and an integrated circuit separately manufactured. Unique fabrication processes are developed, such as the feed-through forming using a dicing process, a planarization of the Benzocyclobutene (BCB) polymer filled in the feed-through and a wafer bonding to stack silicon diaphragm onto ASIC (application specific integrated circuit) wafer. The ASIC used in this paper has a capacitance measurement circuit and a digital communication interface mimicking a tactile receptor of a human. We successfully integrated the force sensor and the ASIC into a 2.5×2.5×0.3 mm die and confirmed autonomously transmitted packets which contain digital sensing data with the linear force sensitivity of 57,640 Hz/N and 10 mN of data fluctuation. A small stray capacitance of 1.33 pF is achieved by use of 10 μm thick BCB isolation layer and this minimum package structure.

Logic-in-memory (LiM) has emerged as a promising paradigm to address the von Neumann bottleneck by integrating data storage and in-situ computation. Resistive random-access memory (RRAM) is a strong candidate for LiM owing to its non-volatility, fast switching characteristics, and compatibility with CMOS integration. However, intrinsic cycle-to-cycle and device-to-device variability fundamentally limits logic reliability in RRAM-based LiM architectures, necessitating well-defined device specifications and variability margins to ensure correct operation. In this work, we experimentally demonstrate a CMOS-integrated TaO x -based 1T1R RRAM computing fabric that supports reconfigurable LiM operations, including a functionally complete Boolean set and in-memory arithmetic primitives. Through extensive statistical measurements and variability-aware statistical modeling, we systematically evaluate the impact of key variability sources, SET voltage ( V SET ), low resistance state, and high resistance state, on logic correctness and identify the dominant contributors to computational failure. Finally, we derive the device specifications and requirements to achieve error-free stateful LiM operations in the 1T1R RRAM arrays.

Visible to short‐wave infrared multispectral imaging is gaining significant attention across various fields, including agriculture, security, and medical diagnostics. Traditional multispectral imaging systems often rely on separate sensors for different spectral bands, leading to complex optical alignment and irreversible resolution loss. Here, we present hardware‐algorithm co‐designed architecture to achieve multispectral super‐resolution imaging. Specifically, we demonstrate a monolithic quad‐spectral photovoltaic imaging platform featuring a resolution of 640 × 512 pixels with <1% dead pixels per channel. The system achieves broadband spectral integration from visible to short‐wave infrared (350–2350 nm) by combining an all‐polymer bulk heterojunction with colloidal quantum dots within a single CMOS‐compatible architecture. The compatibility of all‐polymer bulk heterojunction with direct photopatterning allows for precise patterning and high‐density integration, enabling the devices to operate efficiently in photovoltage mode. To address resolution degradation inherent in planar‐integrated spectral sensing architectures, we applied a super‐resolution reconstruction method, restoring images to a resolution of 640 × 512. The demonstrated capability to simultaneously capture and process multispectral data paves the way for CMOS integration, multispectral Imagers, organic photodetector, super‐resolution reconstruction applications in diverse fields, from precision agriculture to medical diagnostics and beyond. We demonstrate a monolithic quad‐spectral imager that seamlessly integrates visible and short‐wave infrared detection on a single chip. Through direct photopatterning of an all‐polymer bulk heterojunction and colloidal quantum dots, the device achieves high‐resolution (640 × 512) imaging across 350–2400 nm, enabling multispectral capture for applications from precision agriculture to medical diagnostics.

3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system. Monolithically 3D integrated on‐chip neural system is demonstrated using CMOS circuits, considering the degradation of memory window after wafer bonding and interconnection processes. Ag diffusion in bi‐layer is studied in volatile memristors. Additionally, interconnection and gate metal are investigated to reduce defective traps in non‐volatile transistor. A memory window is improved over 106 in both types of devices.