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With the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance. This article proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing.

The floating‐gate transistor is commonly employed as a non‐volatile memory device, leveraging a floating node at its gate to store electrical charge over extended periods. This stored charge effectively alters the threshold voltage of the transistor. Utilizing standard CMOS technologies, floating‐gate transistors can be designed and fabricated using conventional CMOS processes. This study focuses on characterizing the performance of a PMOS‐based floating‐gate transistor, specifically fabricated using the open‐source Skywater 130 nm process. The modulation of charge on the floating node is explored through both hot‐electron injection and Fowler–Nordheim tunnelling, providing insight into the resolution of these programming mechanisms. Additionally, the study includes a preliminary analysis of the retention time of the programmed charge in these devices. This work contributes to the open‐source electronics community by detailing the design and programming techniques of floating‐gate transistors developed with an open‐source process design kit, and makes the corresponding FG cell designs available for public use. The floating‐gate transistor is commonly employed as a non‐volatile memory device, leveraging a floating node at its gate to store electrical charge over extended periods. This study focuses on characterizing the performance of a PMOS‐based floating‐gate transistor, specifically fabricated using the open‐source Skywater 130 nm process—the modulation of charge on the floating node is explored through both hot‐electron injection and Fowler–Nordheim tunnelling, providing insight into the resolution of these programming mechanisms, as well as charge retention over time.

This work proposes a 6T1R non‐volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage‐division (VD)‐based restore process with reduced DC current and (3) a trimmable multi‐cycle (TMC) store process to reduce data backup and recovery errors. We fabricated a 1 kb VD‐6T1R nvSRAM test array with back‐end‐of‐line integrated metal oxide RRAM cells in a 180 nm CMOS process. The reuse of transistors allows the VD‐6T1R cell structure to occupy only 1.14× the area of a standard 6T SRAM cell. The store and restore operations were experimentally verified at the array level. The restore error rates of the fabricated test array can be effectively suppressed using TMC store cycles. The restore errors in the fabricated 1 kb cell array can be eliminated after five cycles. This work proposes a 6T1R non‐volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage‐division (VD)‐based restore process with reduced DC current and (3) a trimmable multi‐cycle store process to reduce data backup and recovery errors. A 1 kb VD‐6T1R nvSRAM test array is demonstrated using 180 nm CMOS process.

The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.

A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS‐based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS‐based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM.

Here a more accurate piecewise approximation (PWA) scheme for non‐linear activation function is proposed. It utilizes a precision‐controlled recursive algorithm to predict a sub‐range; after that, the REMEZ algorithm is used to find the corresponding approximation function. The PWA realized in three ways: using first‐order functions, that is, piecewise linear model, second‐order functions (piecewise non‐linear model), and hybrid‐order model (a mixture of first‐order and second‐order functions). The hybrid‐order approximation employs the second‐order derivative of non‐linear activation function to decide the linear and non‐linear sub‐regions, correspondingly the first‐order and second‐order functions are predicted, respectively. The accuracy is compared to the present state‐of‐the‐art approximation schemes. The multi‐layer perceptron model is designed to implement XOR‐gate, and it uses an approximate activation function. The hardware utilization is measured using the TSMC 0.18‐μm library with the Synopsys Design Compiler. Result reveals that the proposed approximation scheme efficiently approximates the non‐linear activation functions.

A high reliability offset-tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT-MTJ) memory. This circuit, using a triple-stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT-MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance.

The conventional computing system has been facing enormous pressure to cope with the uprising demand for computing speed in today's world. In search of high-speed computing in the nano-scale era, it becomes the utmost necessity to explore a viable alternative to overcome the challenges of the physical limit of complementary-metal-oxide-semiconductor (CMOS). Towards that direction, the processing-in-memory (PIM) is advancing its importance as it keeps the computation as adjacent as possible to memory. It promises to outperform the latencies of the conventional stored-program concept by embedding storage and data computation in a single unit. On the other hand, the bit storing and processing capability of Akers array provides the foundation of PIM. Again, quantum-dot cellular automata (QCA) emerges as a promising nanoelectronic to put back CMOS to give fast-paced devices at the nanoelectronics era. This work presents a novel PIM concept, embedding Akers array in QCA to achieve high-speed computing at the nano-scale era. QCA implementation of universal logic utilizing Akers array signifies its processing power and puts forth its potentials. A universal function is considered for testing the effectiveness of the proposed PIM cell. The performance evaluation indicates the efficacy of QCA PIM over the conventional Von Neumann architecture.

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network-on-chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non-volatile spin transfer torque random access memory (STT-RAM)-based buffers. STT-RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write-variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso-capacity and iso-area-based alternatives to replace SRAM buffers with STT-RAM buffers are also presented. Pure STT-RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.

A five-transistor dynamic ternary content addressable memory (CAM) is presented for high-density data search applications. The data path and the search path are separated to avoid unwanted capacitive coupling at the storage node. To increase the data retention time, the data lines are grounded and dummy search lines are implemented for refresh operations. The proposed CAM cell is fabricated using a 130 nm CMOS process, and occupies an area of 8.99 μm2. A prototype array of 64 × 128 search memory has a retention time of 2.84 ms at room temperature with a 1.2 V supply voltage. The hardware search performance is compared with a conventional software-based search scheme, running on two different systems with clock frequencies of more than an order of magnitude faster. The hardware search engine exhibits comparable search speeds while dissipating only 149 mW.