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Long-term repeating traumatic puncture is required for dialysis therapy, which results in frequent thrombosis and graduate vascular access stenosis, such as inflow or outflow stenosis and coexistence of both. An arteriovenous graft has a higher patency rate than an arteriovenous fistula. This study intends to use the dual-channel auscultation-based non-invasive method to screen inflow and outflow stenoses. Frequency analysis is used to decompose phonoangiography (PAG) signals to frequency features using the different data length of acoustic data. Burg autoregressive method is employed to extract the key frequency parameters from sufficient spectral data, including characteristic frequencies and distinct peaks of power spectral densities (PSDs). In big data processing, PSDs and the degree of stenosis (DOS) have been validated to show a positive correlation with sufficient big spectral data. An intelligent machine learning model, bidirectional hetero-associative memory network (BHAMN), is carried out to identify the level of DOS at the inflow site, the mid-site, or the outflow site of a vascular access. The experimental results will indicate that the proposed intelligent machine learning model has higher hit rates.

A memristor‐transistor hybrid ternary content addressable memory (MTCAM) with a memristor‐based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS‐based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS‐based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM.

The development of IoT applications generally relies on centralized architectures, whether they use solutions based on cloud or on premises environments, usually operated by a single entity. However, recent technologies and the increasing number of interconnected intelligent devices are driving new approaches, the essential requirements being scalability and fault-tolerance. This work studies an alternative concept based on a decentralised architecture useful in several scenarios and focuses on available technologies for potential practical implementations.

Here a more accurate piecewise approximation (PWA) scheme for non‐linear activation function is proposed. It utilizes a precision‐controlled recursive algorithm to predict a sub‐range; after that, the REMEZ algorithm is used to find the corresponding approximation function. The PWA realized in three ways: using first‐order functions, that is, piecewise linear model, second‐order functions (piecewise non‐linear model), and hybrid‐order model (a mixture of first‐order and second‐order functions). The hybrid‐order approximation employs the second‐order derivative of non‐linear activation function to decide the linear and non‐linear sub‐regions, correspondingly the first‐order and second‐order functions are predicted, respectively. The accuracy is compared to the present state‐of‐the‐art approximation schemes. The multi‐layer perceptron model is designed to implement XOR‐gate, and it uses an approximate activation function. The hardware utilization is measured using the TSMC 0.18‐μm library with the Synopsys Design Compiler. Result reveals that the proposed approximation scheme efficiently approximates the non‐linear activation functions.

Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems. This article proposes a NAND‐NOR match‐line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match‐line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND‐MLs) to deactivate redundant NOR‐MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND‐ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match‐line delay of the proposed 64×32‐bit hybrid CAM is 366.90 ps in a standard 45‐nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power‐delay‐product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.

This paper addresses the dilemmas of accessibility, comprehensiveness, and ownership related to health data. To resolve these dilemmas, we propose and justify a novel, globally scalable reference architecture for a Personal Health Data Space (PHDS). This architecture leverages decentralized content-addressable storage (DCAS) networks, ensuring that the data subject retains complete control and ownership of their personal health data. In today's globalized world, where people are increasingly mobile for work and leisure, healthcare is transitioning from episodic symptom-based treatment toward continuity of care. The main aims of this are patient engagement, illness prevention, and active and healthy longevity. This shift, along with the secondary use of health data for societal benefit, has intensified the challenges associated with health data accessibility, comprehensiveness, and ownership. The study is structured around four health data use case scenarios from the Estonian National Health Information System (EHIS): primary medical use, medical emergency use, secondary use, and personal use. We analyze these use cases from the perspectives of accessibility, comprehensiveness, and ownership. Additionally, we examine the security, privacy, and interoperability aspects of health data. The proposed architectural solution allows individuals to consolidate all their health data into a unified Personal Health Record (PHR). This data can come from various healthcare institutions, mobile applications, medical devices for home use, and personal health notes. The comprehensive PHR can then be shared with healthcare providers in a semantically interoperable manner, regardless of their location or the information systems they use. Furthermore, individuals maintain the autonomy to share, sell, or donate their anonymous or pseudonymous health data for secondary use with different systems worldwide. The proposed reference architecture aligns with the principles of the European Health Data Space (EHDS) initiative, enhancing health data management by providing a secure, cost-effective, and sustainable solution.

Performance of a memory depends on the storage stability, yield and sensing speed. Differential input and the latching time of sense amplifiers are considered as primary performance factors in static random access memory. In a content addressable memory (CAM), the sensing is carried out through the matchline (ML) and the time for evaluation is the key to decide the search speed. The density of CAM is on a rise to accommodate a higher amount of information which increases the power dissipation associated with it. Issues such as the logical threshold variation and lower noise margin between match and mismatch are critical in the operation of a CAM. A good ML sensing technique can reduce the ML power with enhanced evaluation speed. This work provides an analogy of various ML sensing techniques based on their pre-charging, evaluation and performance improvement strategies. Estimation on the power dissipation and evaluation time are made and in-depth analysis on their power-speed-overhead trade-off are carried on 64-bit CAM macros.

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

A five-transistor dynamic ternary content addressable memory (CAM) is presented for high-density data search applications. The data path and the search path are separated to avoid unwanted capacitive coupling at the storage node. To increase the data retention time, the data lines are grounded and dummy search lines are implemented for refresh operations. The proposed CAM cell is fabricated using a 130 nm CMOS process, and occupies an area of 8.99 μm2. A prototype array of 64 × 128 search memory has a retention time of 2.84 ms at room temperature with a 1.2 V supply voltage. The hardware search performance is compared with a conventional software-based search scheme, running on two different systems with clock frequencies of more than an order of magnitude faster. The hardware search engine exhibits comparable search speeds while dissipating only 149 mW.

This paper studies known indexing structures from a new point of view: minimisation of data exchange between an IoT device acting as a blockchain client and the blockchain server running a protocol suite that includes two Guy Fawkes protocols, PLS and SLVP. The PLS blockchain is not a cryptocurrency instrument; it is an immutable ledger offering guaranteed non-repudiation to low-power clients without use of public key crypto. The novelty of the situation is in the fact that every PLS client has to obtain a proof of absence in all blocks of the chain to which its counterparty does not contribute, and we show that it is possible without traversing the block’s Merkle tree. We obtain weight statistics of a leaf path on a sparse Merkle tree theoretically, as our ground case. Using the theory we quantify the communication cost of a client interacting with the blockchain. We show that large savings can be achieved by providing a bitmap index of the tree compressed using Tunstall’s method. We further show that even in the case of correlated access, as in two IoT devices posting messages for each other in consecutive blocks, it is possible to prevent compression degradation by re-randomising the IDs using a pseudorandom bijective function. We propose a low-cost function of this kind and evaluate its quality by simulation, using the avalanche criterion.