Explore the vast range of titles available.

The Medium Energy X-ray telescope (ME) is one of the three main telescopes on board the Insight hard X-ray modulation telescope ( Insight- HXMT) astronomy satellite. ME contains 1728 pixels of Si-PIN detectors sensitive in 5–30 keV with a total geometrical area of 952 cm 2 . The application specific integrated circuit (ASIC) chip, VA32TA6, is used to achieve low power consumption and low readout noise. The collimators define three kinds of field of views (FOVs) for the telescope, 1°×4°, 4°×4°, and blocked ones. Combination of such FOVs can be used to estimate the in-orbit X-ray and particle background components. The energy resolution of ME is ~3 keV at 17.8 keV (FWHM) and the time resolution is 255 μs. In this paper, we introduce the design and performance of ME.

With the rapid growth in healthcare demand, an emergent, novel technology called wireless body area networks (WBANs) have become promising and have been widely used in the field of human health monitoring. A WBAN can collect human physical parameters through the medical sensors in or around the patient’s body to realize real-time continuous remote monitoring. Compared to other wireless transmission technologies, a WBAN has more stringent technical requirements and challenges in terms of power efficiency, security and privacy, quality of service and other specifications. In this paper, we review the recent WBAN medical applications, existing requirements and challenges and their solutions. We conducted a comprehensive investigation of WBANs, from the sensor technology for the collection to the wireless transmission technology for the transmission process, such as frequency bands, channel models, medium access control (MAC) and networking protocols. Then we reviewed its unique safety and energy consumption issues. In particular, an application-specific integrated circuit (ASIC)-based WBAN scheme is presented to improve its security and privacy and achieve ultra-low energy consumption.

Deep neural networks (DNNs) have made significant achievements in a wide variety of domains. For the deep learning tasks, multiple excellent hardware platforms provide efficient solutions, including graphics processing units (GPUs), central processing units (CPUs), field programmable gate arrays (FPGAs), and application-specific integrated circuit (ASIC). Nonetheless, CPUs outperform other solutions including GPUs in many cases for the inference workload of DNNs with the support of various techniques, such as the high-performance libraries being the basic building blocks for DNNs. Thus, CPUs have been a preferred choice for DNN inference applications, particularly in the low-latency demand scenarios. However, the DNN inference efficiency remains a critical issue, especially when low latency is required under conditions with limited hardware resources, such as embedded systems. At the same time, the hardware features have not been fully exploited for DNNs and there is much room for improvement. To this end, this paper conducts a series of experiments to make a thorough study for the inference workload of prominent state-of-the-art DNN architectures on a single-instruction-multiple-data (SIMD) CPU platform, as well as with widely applicable scopes for multiple hardware platforms. The study goes into depth in DNNs: the CPU kernel-instruction level performance characteristics of DNNs including branches, branch prediction misses, cache misses, etc, and the underlying convolutional computing mechanism at the SIMD level; The thorough layer-wise time consumption details with potential time-cost bottlenecks; And the exhaustive dynamic activation sparsity with exact details on the redundancy of DNNs. The research provides researchers with comprehensive and insightful details, as well as crucial target areas for optimising and improving the efficiency of DNNs at both the hardware and software levels.

Significance: Time-domain functional near-infrared spectroscopy (TD-fNIRS) has been considered as the gold standard of noninvasive optical brain imaging devices. However, due to the high cost, complexity, and large form factor, it has not been as widely adopted as continuous wave NIRS systems. Aim: Kernel Flow is a TD-fNIRS system that has been designed to break through these limitations by maintaining the performance of a research grade TD-fNIRS system while integrating all of the components into a small modular device. Approach: The Kernel Flow modules are built around miniaturized laser drivers, custom integrated circuits, and specialized detectors. The modules can be assembled into a system with dense channel coverage over the entire head. Results: We show performance similar to benchtop systems with our miniaturized device as characterized by standardized tissue and optical phantom protocols for TD-fNIRS and human neuroscience results. Conclusions: The miniaturized design of the Kernel Flow system allows for broader applications of TD-fNIRS.

The Sri Lankan leopard (Panthera pardus kotiya) is an endangered subspecies restricted to isolated and fragmented populations in Sri Lanka. Among them, melanistic leopards have been recorded on a few occasions. Literature suggests the evolution of melanism several times in the Felidae family, with three species having distinct mutations. Nevertheless, the mutations or other variations in the remaining species, including Sri Lankan melanistic leopard, are unknown. We used reference-based assembled nuclear genomes of Sri Lankan wild type and melanistic leopards and de novo assembled mitogenomes of the same to investigate the genetic basis, adaptive significance, and evolutionary history of the Sri Lankan melanistic leopard. Interestingly, we identified a single nucleotide polymorphism in exon-4 Sri Lankan melanistic leopard, which may completely ablate Agouti Signalling Protein (ASIP) function. The wild type leopards in Sri Lanka did not carry this mutation, suggesting the cause for the occurrence of melanistic leopords in the population. Comparative analysis of existing genomic data in the literature suggests it as a P. p. kotiya specific mutation and a novel mutation in the ASIP-gene of the Felidae family, contributing to naturally occurring colour polymorphism. Our data suggested the coalescence time of Sri Lankan leopards at ~0.5 million years, sisters to the Panthera pardus lineage. The genetic diversity was low in Sri Lankan leopards. Further, the P. p. kotiya melanistic leopard is a different morphotype of the P. p. kotiya wildtype leopard resulting from the mutation in the ASIP-gene. The ability of black leopards to camouflage, along with the likelihood of recurrence and transfer to future generations, suggests that this rare mutation could be environment-adaptable.

Convolutional Neural Networks (CNNs) generally suffer from excessive computational overhead, high resource consumption, and complex network structures, which severely restrict the deployment on microprocessor chips. Existing related accelerators only have an energy efficiency ratio of 2.32–6.5925 GOPs/W, making it difficult to meet the low-power requirements of embedded application scenarios. To address these issues, this paper proposes a low-power and high-energy-efficiency CNN accelerator architecture based on a central processing unit (CPU) and an Application-Specific Integrated Circuit (ASIC) heterogeneous computing architecture, adopting an operator-fused systolic array algorithm with the YOLOv5n target detection network as the application benchmark. It integrates a 2D systolic array with Conv-BN fusion technology to achieve deep operator fusion of convolution, batch normalization and activation functions; optimizes the RISC-V core to reduce resource usage; and adopts a locking mechanism and a prefetching strategy for the asynchronous platform to ensure operational stability. Experiments on the Nexys Video development board show that the architecture achieves 20.6 GFLOPs of computational performance, 1.96 W of power consumption, and 10.46 GOPs/W of energy efficiency ratio, which is 58–350% higher than existing mainstream accelerators, thus demonstrating excellent potential for embedded deployment.

With the evolution of synchrotron light sources to fourth generation (diffraction-limited storage rings), the brilliance is increased by several orders of magnitude compared to third generation facilities. For example, the Swiss Light Source (SLS) has been upgraded to SLS 2.0, promising a horizontal emittance reduced by a factor of 40, and a brilliance up to two orders of magnitude (three at higher energies). A key challenge arising from the increased flux is the heightened accumulated dose in silicon sensors, which leads to a significant increase in radiation damage. This translates into an increase of both noise and dark current, as well as a reduction in the dynamic range for long exposure times, thus affecting the performance of the detector, in particular, for charge-integrating detectors. We have designed sensors with a 4 × 4 mm2 pixel array featuring 16 design variations of 25 µm pitch pixels with different implant and metal sizes and tested them bump-bonded to MÖNCH 0.3, a charge integrating hybrid pixel detector readout ASIC. Following a first assessment of the functionality and performance of the different pixel designs, the assembly has been irradiated with X-rays. The variation in the tested parameters was characterized at different accumulated doses up to 100 kGy at the sensor entrance window side. The annealing dynamics at room temperature have also been measured. The results show that the default pixel design is currently not optimal and can benefit from layout changes (reduction in the inter-pixel gap area with full metal coverage of the implant). Further studies on the metal coverage over large implants could be conducted. The layout changes are, however, not sufficient for future full-sized sensors, requiring improved radiation hardness and long-term stability, and additional strategies such as focusing on detector cooling and changes in sensor technologies would be required.

Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers −1,1. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and inference and reduces hardware complexity and model sizes for implementation. Compared to traditional deep learning architectures, BNNs are a good choice for implementation in resource-constrained devices like FPGAs and ASICs. However, BNNs have the disadvantage of reduced performance and accuracy because of the tradeoff due to binarization. Over the years, this has attracted the attention of the research community to overcome the performance gap of BNNs, and several architectures have been proposed. In this paper, we provide a comprehensive review of BNNs for implementation in FPGA hardware. The survey covers different aspects, such as BNN architectures and variants, design and tool flows for FPGAs, and various applications for BNNs. The final part of the paper gives some benchmark works and design tools for implementing BNNs in FPGAs based on established datasets used by the research community.

Timepix3 detectors are the latest generation of hybrid active pixel detectors of the Medipix/Timepix family. Such detectors consist of an active sensor layer which is connected to the readout ASIC (application specific integrated circuit), segmenting the detector into a square matrix of 256 × 256 pixels (pixel pitch 55 μ m). Particles interacting in the active sensor material create charge carriers, which drift towards the pixelated electrode, where they are collected. In each pixel, the time of the interaction (time resolution 1.56 ns) and the amount of created charge carriers are measured. Such a device was employed in an experiment in a 120 GeV/c pion beam. It is demonstrated, how the drift time information can be used for “4D” particle tracking, with the three spatial dimensions and the energy losses along the particle trajectory (dE/dx). Since the coordinates in the detector plane are given by the pixelation ( x , y ), the x - and y -resolution is determined by the pixel pitch (55  μ m). A z -resolution of 50.4 μ m could be achieved (for a 500 μ m thick silicon sensor at 130 V bias), whereby the drift time model independent z -resolution was found to be 28.5  μ m.

Wearable devices can be developed using hardware platforms such as Application Specific Integrated Circuits (ASICs), Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), Micro controller Units (MCUs), or Field Programmable Gate Arrays (FPGAs), each with distinct advantages and limitations. ASICs offer high efficiency but lack flexibility. GPUs excel in parallel processing but consume significant power. DSPs are optimized for signal processing but are limited in versatility. CPUs provide low power consumption but lack computational power. FPGAs are highly flexible, enabling powerful parallel processing at lower energy costs than GPUs but with higher resource demands than ASICs. The combined use of FPGAs and CPUs balances power efficiency and computational capability, making it ideal for wearable systems requiring complex algorithms in far-edge computing, where data processing occurs onboard the device. This approach promotes green electronics, extending battery life and reducing user inconvenience. The primary goal of this work was to develop a versatile framework, similar to existing software development frameworks, but specifically tailored for mixed FPGA/MCU platforms. The framework was validated through a real-world use case, demonstrating significant improvements in execution speed and power consumption. These results confirm its effectiveness in developing green and smart wearable systems.