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result(s) for
"Data hiding. Hardware-Security"
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A Novel Architecture of Masked Logic Cells for Side-Channel Attacks
by
Shippu Sachdeva
,
Manoj Sindhwani
,
Abhishek Kumar
in
Correlation
,
Data hiding. Hardware-Security
,
Mask Cell
2024
Side-channel attacks are attacks against cryptographic devices that are based on information obtained by leakage into cryptographic algorithm hardware implementation rather than algorithm implementation. Power attacks are based on analyzing the power consumption of a corresponding input and obtaining access to this method. The power profile of the encryption circuit maintains an interaction with the input to be processed, allowing the attacker to guess the hidden secrets. In this work, we presented a novel architecture of masked logic cells that are resistant to power attacks and have reduced cell numbers. The presented masking cell reduces the relationship between the actual power and the mathematically approximated power model measured by the Pearson correlation coefficient. The security aspect of the logic cell is measured with the correlation coefficient of the person. The proposed mask-XOR and mask-AND cells are 0.0053 and 0.3respectively, much lower than the standard XOR and AND cells of 0.134 and 0.372respectively.
Journal Article
Low-Cost Full Correlated-Power-Noise Generator to Counteract Side-Channel Attacks
by
Tena-Sánchez, Erica
,
Acosta, Antonio J.
,
Potestad-Ordóñez, Francisco Eugenio
in
Accountants
,
Analysis
,
Architecture
2025
Considerable attention has been given to addressing side-channel attacks to improve the security of cryptographic hardware implementations. These attacks encourage the exploration of various countermeasures across different levels of abstraction, through masking and hiding techniques, mainly. In this paper, we introduce a novel hiding countermeasure designed to mitigate Correlation Power Analysis (CPA) attacks without significant overhead. The new countermeasure interferes with the processed data, minimizing the power correlation with the secret key. The proposed method involves using a Correlated-Power-Noise Generator (CPNG). This study is supported by experimental results using CPA attacks on a SAKURA-G board with a SPARTAN-6 Xilinx FPGA. An Advanced Encryption Standard (AES) cipher with 128/256-bit key size is employed for this purpose. The proposed secure design of AES has an area overhead of 29.04% compared to unprotected AES. After conducting a CPA attack, the acquisition of information about the private key has been reduced drastically by 44.5%.
Journal Article