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Model order reduction technique provides an effective way to reduce computational complexity in large-scale circuit simulations. This paper proposes a new model order reduction method for delay circuit systems based on Hermite expansion technique. The presented method consists of three steps i.e., first the delay elements are approximated using the recursive relation of Hermite polynomials, then in the second step, the reduced order is estimated for the delay circuit system using a delay truncation in the Hermite domain and in the third step, a multi-order Arnoldi process is computed for obtaining the projection matrix. In the following, the reduced order delay circuit model is obtained by the projection matrix. Moment matching and passivity properties of the reduced circuit system are also analyzed. Two circuit examples with delay components are performed to verify the effectiveness of the proposed MOR approach.

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 n m CMOS. The ADC occupies 0.054 m m 2 and achieves an SNDR of 57.4 dB under 67 μ W power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.

Field programmable gate arrays (FPGAs) are adopted in many electronic systems, due to their design flexibility and high performance. For providing right FPGAs for different applications, FPGA architectural exploration is needed. Accurate estimation of area and delay of low‐level FPGA circuits is required to evaluate different architecture candidates during the exploration. In this study, the authors present a fast and accurate delay model by extracting the key parameters affecting FPGA delay and by combining the classical Elmore equivalent model and the powerful learning capability of neural network. The derived model can be integrated with the existing FPGA architecture exploration flow perfectly. Experimental results show that compared with circuit simulator tool HSPICE, this model speeds up the delay estimation by 2863 times with the average error of 1.9% during the architectural exploration process. This fast and accurate estimation allows FPGA architects to explore more architectural options in limited time, resulting in optimised FPGA architecture.

Ferrimagnets having low RF loss are used in passive microwave components such as isolators, circulators, phase shifters, and miniature antennas operating in a wide range of frequencies (1–100 GHz) and as magnetic recording media owing to their novel physical properties. Frequency tuning of these components has so far been obtained by external magnetic fields provided by a permanent magnet or by passing current through coils. However, for high frequency operation the permanent part of magnetic bias should be as high as possible, which requires large permanent magnets resulting in relatively large size and high cost microwave passive components. A promising approach to circumvent this problem is to use hexaferrites, such as BaFe 12 O 19 and SrFe 12 O 19 , which have high effective internal magnetic anisotropy that also contributes to the permanent bias. Such a self-biased material remains magnetized even after removing the external applied magnetic field, and thus, may not even require an external permanent magnet. In garnet and spinel ferrites, such as Y 3 Fe 5 O 12 (YIG) and MgFe 2 O 4 , however, the uniaxial anisotropy is much smaller, and one would need to apply huge magnetic fields to achieve such high frequencies. In Part 1 of this review of microwave ferrites a brief discussion of fundamentals of magnetism, particularly ferrimagnetism, and chemical, structural, and magnetic properties of ferrites of interest as they pertain to net magnetization, especially to self biasing, are presented. Operational principles of microwave passive components and electrical tuning of magnetization using magnetoelectric coupling are discussed in Part 2.

With the advent of nanoscale devices, due to the problems of leakage power has grown enormously. Reducing leakage power is one of the main challenges in the design of low power circuits. This study presents a delay efficient circuit level leakage reduction technique, which uses dual‐Vth named ‘Feedback Sleeper‐Stack (FS‐S)’ for deep submicron (DSM) technology. FS‐S is proposed in order to reduce leakage power dramatically while saving exact logic state. An analytical RC delay model of the FS‐S is derived. Comparisons are then carried out in terms of leakage power, total power, delay, area, and power–delay product to the available leakage reduction techniques. 45 nm BSIM4 Predictive Technology Model parameters are used to estimate the changes in power and delay. FS‐S is applied to three generic logic circuits to show that the proposed technique is suitable for general logic circuits. Results show that chain of four inverters, NAND3 gate, and C17 circuit with dual‐Vth FS‐S give 15, 62, and 90% performance levels, respectively, over base case circuit under iso‐area condition.

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. A novel dynamic bias latch‐type comparator, preceded by a voltage‐controlled delay line, is presented for high‐speed and energy‐efficient analog‐to‐digital converter applications. It demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells.

A 600 V high-voltage gate drive IC (HVIC) using a novel robust isolation structure and a new delay circuit with low-temperature coefficient is proposed in this study. The novel isolation structure features with n−-well islands alternatively arranged in the p-well region and its breakdown voltage is improved by about 7% (from 690 to 740 V) compared with the conventional isolation because of that the electrical field crowed in the p-well corner is ameliorated. The presented delay circuit used in the gate drive IC is composed of a temperature-insensitive ramp generator and a comparator. The typical turn-on/-off propagation delay time of the HVIC is 95 ns/85 ns and its maximum temperature coefficient is only 0.065 ns/°C.

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

This paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. This paper propose a small‐area and low‐power all‐digital duty cycle corrector with de‐skew. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of circuit.

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.