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Multipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hardware resources, particularly in applications where that can tolerate minimal accuracy loss. Achieving higher multiplier performance typically requires a careful trade-off between hardware complexity and computational precision. One widely adopted method for designing approximate multipliers involves replacing exact compressors with their approximate counterparts, resulting in a trade-off with accuracy. This paper introduces novel approximate multiplier architectures that partition the computation into three distinct regions: accurate, approximate, and lower region. Partial product compression in the approximate region is carried out using the proposed two 4:2 compressors combined with conventional arithmetic circuits like half adder, full adder and OR logic, to produce the final product. The proposed compressors are developed by analyzing the input occurrence probability of all possible combinations with trade-off between hardware efficiency and computational accuracy. To further improve accuracy, an error correction logic is developed to compensate for inaccuracies in specific input scenarios. Several benchmark error metrics and hardware synthesis using a 32-nm CMOS technology are evaluated for the proposed designs through simulations. Notably, the results of the proposed approximate multipliers shows an average improvements of 70.6% in accuracy, 60.4% in Energy-Delay Product, 30.9% in Power-Delay Product, and 41.6% in delay, outperforming all existing designs considered for comparison. Furthermore, real-time image multiplication experiments were performed using multiple benchmark image datasets, and the output quality was evaluated through the Similarity Index Metric (SSIM) and Peak Signal-to-Noise Ratio (PSNR). In addition, detailed error and heat-map visual analyses were conducted to examine the spatial distribution and intensity of computational errors across pixels. The results demonstrate that the proposed multiplier consistently achieves higher SSIM and PSNR values, along with significantly reduced error concentrations, outperforming existing approximate multiplier designs.

It is difficult for students and teachers to detect and correct logic errors in source code. Compilers and integrated development environments (IDEs) have the ability to detect and correct syntax errors but it is also difficult for them to detect and correct logic errors. Although many machine learning approaches have been proposed that can show correction candidates for logic errors, they do not provide guidance concerning how the user should fix them. In this paper, we propose a model for correcting logic errors in a given source code. The proposed model realizes debugging of multiple logic errors in the source code by iterative trials of identifying the errors, correcting the errors, and testing the source code. In this model, in the first stage, a list of correction candidates is provided by a deep learning model, and then the list is given to an editing operation predictor that predicts the editing operation for the correction candidate. To learn the internal parameters of the proposed model, we use a set of solution codes created to solve the corresponding programming tasks in a real e-learning system. To verify the usefulness of the proposed model, we apply it to 32 programming tasks. Experimental results show that the correction accuracy is, on average, 58.64% higher than that of the conventional model without iterative trials.

An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter with a 45 nm CMOS process is described. In order to improve the non-linearity error of a conventional folding amplifier, a new symmetrical zero-crossing technique is proposed. Further, a digital error correction logic to rectify the distortion errors of analog blocks is also discussed. The proposed chip has been fabricated with 1.2 V 45 nm Samsung CMOS technology. The effective chip area is 1.98 mm2 and the power dissipation is about 80 mW. The measured result of SNDR is about 38 dB, when the input frequency is 1 GHz at the sampling frequency of 2 GS/s. The measured INL is within +2.5 LSB/−2.0 LSB and DNL is within +1.0 LSB/−1.0 LSB.

This paper presents an optimising model for integrating the traditional reliability prediction methodology with simple analytical techniques to facilitate the designer to decide upon the memory fault-tolerant choices of an onboard computer. In this exercise, the hardware reliability estimates of a circuit without any error correction as well as that of a circuit with error detection and correction were calculated. The failure rates of each component and soldering have been accounted for in these prediction procedures. A suitable probability distribution is chosen for data errors and is analytically combined with the hardware reliability predictions to study the trade-offs. An optimum strategy for introducing the hardware error correction logic in the circuit is presented.

To run large-scale algorithms on a quantum computer, error-correcting codes must be able to perform a fundamental set of operations, called logic gates, while isolating the encoded information from noise 1 – 8 . We can complete a universal set of logic gates by producing special resources called magic states 9 – 11 . It is therefore important to produce high-fidelity magic states to conduct algorithms while introducing a minimal amount of noise to the computation. Here we propose and implement a scheme to prepare a magic state on a superconducting qubit array using error correction. We find that our scheme produces better magic states than those that can be prepared using the individual qubits of the device. This demonstrates a fundamental principle of fault-tolerant quantum computing 12 , namely, that we can use error correction to improve the quality of logic gates with noisy qubits. Moreover, we show that the yield of magic states can be increased using adaptive circuits, in which the circuit elements are changed depending on the outcome of mid-circuit measurements. This demonstrates an essential capability needed for many error-correction subroutines. We believe that our prototype will be invaluable in the future as it can reduce the number of physical qubits needed to produce high-fidelity magic states in large-scale quantum-computing architectures. A scheme to prepare a magic state, an important ingredient for quantum computers, on a superconducting qubit array using error correction is proposed that produces better magic states than those that can be prepared using the individual qubits of the device.

The color code is a topological quantum error-correcting code supporting a variety of valuable fault-tolerant logical gates. Its two-dimensional version, the triangular color code, may soon be realized with currently available superconducting hardware despite constrained qubit connectivity. To guide this experimental effort, we study the storage threshold of the triangular color code against circuit-level depolarizing noise. First, we adapt the Restriction Decoder to the setting of the triangular color code and to phenomenological noise. Then, we propose a fault-tolerant implementation of the stabilizer measurement circuits, which incorporates flag qubits. We show how information from flag qubits can be used in an efficient and scalable way with the Restriction Decoder to maintain the effective distance of the code. We numerically estimate the threshold of the triangular color code to be 0.2%, which is competitive with the thresholds of other topological quantum codes. We also prove that 1-flag stabilizer measurement circuits are sufficient to preserve the full code distance, which may be used to find simpler syndrome extraction circuits of the color code.

Suppressing errors is the central challenge for useful quantum computing 1 , requiring quantum error correction (QEC) 2 – 6 for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy 2 – 4 , poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays 7 , our system combines high two-qubit gate fidelities 8 , arbitrary connectivity 7 , 9 , as well as fully programmable single-qubit rotations and mid-circuit readout 10 – 15 . Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code 6 distance from d  = 3 to d  = 7, preparation of colour-code qubits with break-even fidelities 5 , fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks 16 , 17 , we realize computationally complex sampling circuits 18 with up to 48 logical qubits entangled with hypercube connectivity 19 with 228 logical two-qubit gates and 48 logical CCZ gates 20 . We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling 21 , 22 . These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors. A programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits is described, in which improvement of algorithmic performance using a variety of error-correction codes is enabled.

We present a 1D repetition code based on the so-called cat qubits as a viable approach toward hardware-efficient universal and fault-tolerant quantum computation. The cat qubits that are stabilized by a two-photon driven-dissipative process exhibit a tunable noise bias where the effective bit-flip errors are exponentially suppressed with the average number of photons. We propose a realization of a set of gates on the cat qubits that preserve such a noise bias. Combining these base qubit operations, we build, at the level of the repetition cat qubit, a universal set of fully protected logical gates. This set includes single-qubit preparations and measurements, not, controlled-not, and controlled-controlled-not (Toffoli) gates. Remarkably, this construction avoids the costly magic state preparation, distillation, and injection. Finally, all required operations on the cat qubits could be performed with slight modifications of existing experimental setups.

Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. Here we realize a suite of logical operations on a distance-2 surface code qubit built from seven physical qubits and stabilized using repeated error-detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes. Large-scale quantum computers will manipulate quantum information encoded in error-corrected logical qubits. A complete set of operations has now been realized on a logical qubit with error detection.

Quantum error correction is essential for realizing the full potential of large-scale quantum information processing devices 1 , 2 . Fundamental to its experimental realization is the repetitive detection of errors via projective measurements of quantum correlations among qubits, as well as corrections using conditional feedback 3 . Repetitive application of such tasks requires that they neither induce unwanted crosstalk nor impede further control operations, which is challenging owing to the need to dissipatively couple qubits to the classical world for detection and reinitialization. For trapped ions, state readout involves scattering large numbers of resonant photons, which increases the probability of stray light causing errors on nearby qubits and leads to undesirable recoil heating of the ion motion. Here we demonstrate up to 50 sequential measurements of correlations between two beryllium ion microwave qubits using an ancillary optical qubit in a calcium ion, and implement feedback that allows us to stabilize two-qubit subspaces as well as Bell states, a class of maximally entangled states. Multi-qubit mixed-species gates are used to transfer information within the register from the qubit to the ancilla, enabling readout with negligible crosstalk to the data qubits. Heating of the ion motion during detection is mitigated by recooling all three ions using light that interacts with only the calcium ion, known as sympathetic cooling. A key element of our experimental setup is a powerful classical control system that features flexible in-sequence processing for feedback control. The methods employed here provide essential tools for scaling trapped-ion quantum computing, quantum-state control and entanglement-enhanced quantum metrology 4 . A multi-qubit mixed-species register is used for repeated correlation measurements using conditional feedback to stabilize two-qubit subspaces and Bell states, achieving up to 50 sequential measurements with negligible crosstalk.