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Multiplication is a fundamental mathematical operation that finds extensive applications across various disciplines, particularly in computation-intensive and error-resilient applications, such as image processing. As hardware circuits become more complex, there is a growing demand for approximation circuit methods. Implementation of approximate multipliers has the potential to yield substantial reductions in hardware costs while maintaining acceptable performance levels. Most current designs for approximate multipliers are optimized for ASIC-based circuits, which may not produce similar performance improvements when adapted for FPGA-based circuits. Additionally, many of these existing multiplier designs are limited to unsigned numbers. This paper proposes a novel approach for designing signed approximate multipliers tailored specifically for FPGAs. Two efficient architectures are introduced that efficiently utilize key FPGA components, such as LUTs and Carry4 primitives, by designing the optimal LUT-Carry4 netlists. A Pareto-based analysis is also performed to balance trade-offs and achieve a low mean error distance (MED). Simulation results confirm that the proposed architectures offer superior performance compared to existing signed approximate multipliers, delivering improved power efficiency, reduced resource usage, shorter critical path delay (CPD), and enhanced computational accuracy. The practical applicability of these approximate multipliers is further validated through their use in image processing applications.

Approximate computing is a new approach to reducing power consumption and complexity, increasing performance, and can generate a trade-off between accuracy and power-delay-area efficiency in error-resilient applications. As multiplication is applied in multimedia processing, and it is time-consuming, implementing efficient circuits for multipliers is essential. This article presents novel recursive approximate multipliers and new approximate multipliers based on partial products grouping (clustering). These proposed approximate multipliers are applied in the structure of error-resilient image processing applications: image multiplication, image sharpening, and smoothing. Application-level simulation results show that the proposed multipliers improve the accuracy of their counterparts, while the circuit-level simulation results demonstrate acceptable delay and power consumption. Three Figures Of Merit (FOMs) were introduced to compromise between circuit evaluation criteria and error analysis metrics. By examining these FOMs, the proposed circuits have created a suitable trade-off between circuit and error evaluation criteria compared to other circuits.

The multiplier is one of the most essential arithmetic blocks in computer architecture, as it has an impact on the system’s overall performance. Approximate computing help in improving multiplier performance with low power consumption at the expense of computing precision. In this paper, approximate novel compressors are proposed and further used for the implementation of the proposed approximate multiplier. In the multiplication, process compressors are used for the reduction of partial products with low consumption of power. In comparison to the exact multiplier, the proposed multiplier shows efficient results in terms of Look-up tables, area, memory utilization, and power consumption. The validation of the approximate multiplier is done in an error-tolerant application. In this paper, validation is done in an image processing application for image blending which results in 23.87 dB and 22.7 PSNR values for set 1 and set 2 respectively.

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.

Multipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hardware resources, particularly in applications where that can tolerate minimal accuracy loss. Achieving higher multiplier performance typically requires a careful trade-off between hardware complexity and computational precision. One widely adopted method for designing approximate multipliers involves replacing exact compressors with their approximate counterparts, resulting in a trade-off with accuracy. This paper introduces novel approximate multiplier architectures that partition the computation into three distinct regions: accurate, approximate, and lower region. Partial product compression in the approximate region is carried out using the proposed two 4:2 compressors combined with conventional arithmetic circuits like half adder, full adder and OR logic, to produce the final product. The proposed compressors are developed by analyzing the input occurrence probability of all possible combinations with trade-off between hardware efficiency and computational accuracy. To further improve accuracy, an error correction logic is developed to compensate for inaccuracies in specific input scenarios. Several benchmark error metrics and hardware synthesis using a 32-nm CMOS technology are evaluated for the proposed designs through simulations. Notably, the results of the proposed approximate multipliers shows an average improvements of 70.6% in accuracy, 60.4% in Energy-Delay Product, 30.9% in Power-Delay Product, and 41.6% in delay, outperforming all existing designs considered for comparison. Furthermore, real-time image multiplication experiments were performed using multiple benchmark image datasets, and the output quality was evaluated through the Similarity Index Metric (SSIM) and Peak Signal-to-Noise Ratio (PSNR). In addition, detailed error and heat-map visual analyses were conducted to examine the spatial distribution and intensity of computational errors across pixels. The results demonstrate that the proposed multiplier consistently achieves higher SSIM and PSNR values, along with significantly reduced error concentrations, outperforming existing approximate multiplier designs.

The mesh structure of ad hoc networks, provides the possibility of establishing two disjoint paths from a sender to a receiver. Transmission of video over such networks due to their unpredictability and difficulty in securing reliable channels is challenging. Layered Coding (LC) and Multiple Description Coding (MDC) are two different techniques which can benefit from path diversity for robust video communication and also to adapt with preferences of users\\network. This paper presents an approach to provide error resilient video transmission over a variety of network conditions and applications needs using combined LC and MDC schemes. In the proposed method two descriptions of each layer are generated in the FMO format of the H.264/AVC standard. Unlike the conventional approaches, in our work macroblocks of each layer are divided into two paths. Hence, in the bursty error conditions the error will be smoothly spread in all layers. For better protection and more network compatibility, the base layer is data partitioned and its important part (DP_A) is repeated in both paths. Simulation results show transmission of duplicated DP_A and the non-corresponding descriptions of two layers together on disjoint paths, can improve the error concealment of the decoder and consequently enhance video quality by up to 2 dB.

In this paper, a reliable video communication system using adaptive Hierarchical QAM (HQAM) is designed to provide optimized unequal error protection (UEP) to embedded video bitstreams. Based on the relative importance of bits, video bitstream is partitioned into two priorities, namely High Priority (HP) and Low Priority (LP) substreams. Then, the optimal value of modulation (or hierarchical) parameter ( α ) of HQAM, which controls the relative error protection of these substreams, is selected from a pre-designed look-up table. The proposed system adapts itself by adapting the optimal α according to the varying channel condition, without changing the modulation level. This is in contrast to conventional WiMAX and LTE systems, in which dynamic switching among multiple modulations is used to adapt the varying channel conditions. This paper proposes HQAM with adaptive α as an alternative to the multiple modulation schemes. Moreover, for fixed average transmission power, receiver demodulates symbols without the knowledge of α . In order to further improve the video quality and to reduce the effects of erroneously received LP bits, the proposed system uses another level of adaptation, in which received LP bits are adaptively considered or discarded, before decoding the video, depending on the channel conditions (or optimized α ). Simulation results show that proposed system can achieve significant improvement in the video quality compared to QAM based EEP scheme and non-adaptive HQAM.

To improve the quality of video transmission, a fast error resilience coding method based on frame level rate-distortion analysis is proposed. To constrain the accumulated error propagation distortion and error concealment distortion simultaneously, reference frame selection and intra/inter mode decision are jointly used with redundant pictures. An adaptive multiple redundant picture (AMRP) coding mechanism is used for redundant picture coding with the adaptively estimated number of redundant pictures and encoding parameter for each specific redundant picture. The encoding parameters of different frames are adjusted based on the distortion propagation. We propose a statistical model for efficiently estimating the distortion and rate of the primary and the redundant picture. The total distortion and rate of the primary and the redundant picture are then formulated as a function of the quantization parameter, the temporal prediction distance, and the error resilient configuration. Lastly, the end-to-end rate-distortion optimized selection of the encoding parameters and coding structure is efficiently performed considering error propagation. Experimental results demonstrate that the proposed algorithm exhibits significant performance gains over the state-of-the-art error-resilient encoding methods.