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Data Transfer to Remote GPUs Over High-Performance Networks
Rate of transferring data is one of the most important aspects in science especially when it comes to high computation performance. In most cases, the prerequisite of computations is data while data occasionally not stored locally, it needs to be transferred remotely. Thus, finding the best way to transfer data into the computation location (GPU) plays a critical role in performance of computations. Different methods applied in transferring data implementing Open MPI with CUDA libraries and Mellanox hardware are chosen in this paper for demonstration. The results, remote data can be achieved as fast as local data or faster when using Remote Direct Memory Access (RDMA) or RDMA Over Converged Ethernet (RoCE).
Journal Article
Design of Clock Synchronization of Base Station by Using 8A34002
The stability of the entire base station depends on the synchronization of the base station’s clock. The clock synchronization management chip 8A34002 supports SyncE Ethernet and IEEE 1588. In this architecture, the GPS receiver, SSI, and master/slave switching device all emit PPS/TOD signals. PPS/TOD signals are input into the FPGA, which outputs one PPS/TOD signal. The PPS/TOD signal enters 8A34002 in this design scheme, and the DPLL of 8A34002 provides filtering and clock-following output. The 8A34002‘s signal output is used as the system’s clock after processing. The switching chip, X86 main control chip, and BBU base station board are all driven by the system clock, which serves as a reference clock. The 8A34002 uses four DPLLs, one each for the SyncE, PTP, GNSS, and test functions.
Journal Article
Design Methodology of Automotive Time-Sensitive Network System Based on OMNeT++ Simulation System
Advances in automotive technology require networks to support a variety of communication requirements, such as reliability, real-time performance, low jitter, and strict delay limits. Time-Sensitive Network (TSN) is a keyframe transmission delay-guaranteed solution based on the IEEE 802 architecture of the automotive Ethernet. However, most of the existing studies on automotive TSN performance are based on a single mechanism, lacking a complete and systematic research tool. At the same time, the design method should be considered from a global perspective when designing an automotive TSN system, rather than only considering a single mechanism that TSN applies to. This paper discusses the correspondence between traffic types and automotive scenarios and proposes a methodology to target the delay constraint of traffic types as the design goal of automotive TSN networks. To study the performance of automotive TSN under different mechanisms such as time-aware shaper (TAS), credit-based shaper (CBS), cyclic queuing and forwarding (CQF), etc., this paper also develops a systematic automotive TSN simulation system based on OMNeT++. The simulation system plays a crucial role in the whole methodology, including all applicable TSN standards for the automotive field. Lastly, a complex automotive scenario based on zonal architecture provided by a major motor company in Shanghai is analyzed in the simulated system; verifying TSN can guarantee real-time performance and reliability of the in-vehicle network.
Journal Article