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This paper presents a novel Double Buried-Window Junctionless Field-Effect Transistor (DBW-FET) designed for high-sensitivity, label-free biosensing applications. The proposed device integrates two buried windows, one N-type and one P-type, beneath the active channel within the buried oxide layer, along with two nanocavities serving as biomolecular recognition sites. The dual buried windows form two depletion regions that enhance electrostatic coupling, suppress short-channel effects, and improve biomolecular sensitivity. Numerical simulations using Silvaco TCAD Atlas were performed to investigate device performance under various biomolecular binding conditions. Results show that the DBW-FET exhibits higher drain current, lower subthreshold swing, and improved sensitivity compared with a conventional junctionless FET (C-FET). Furthermore, a machine-learning-assisted optimization framework employing Gaussian Process Regression (GPR) and Bayesian Optimization (BO) was implemented to identify optimal buried window parameters. The optimized design achieved a 20–25% improvement in current sensitivity while maintaining low leakage. These findings demonstrate that the proposed DBW-FET offers a promising and Complementary Metal-Oxide-Semiconductor (CMOS)-compatible architecture for next-generation nanoscale biosensors.

Purpose Optimal endometrial preparation is essential for the transfer of a euploid embryo. Recent works have shown advantages of ovulatory cycle frozen-thawed embryo transfer (Ovu-FET) for simplicity, implantation rate, and reduction of hypertensive disorders of pregnancy; however, few women over age 40 years were included in these studies. This study compared pregnancy outcomes in patients aged 40–45 years between Ovu-FET and programmed cycle FET (PC-FET). Methods Retrospective cohort study in a university-affiliated fertility center. Two hundred eighty-seven FET cycles with euploid embryo transfer between 2015 and 2022 were included, with 116 cycles utilizing the PC-FET and 171 the Ovu-FET protocol. The use of letrozole was permitted for patients with irregular cycles. The primary outcome was ongoing pregnancy rate with secondary outcomes including pregnancy rate, clinical pregnancy rate, biochemical rate, and clinical loss rate. Multivariate regression was utilized to adjust for potential covariates. Results The ongoing pregnancy rates were similar between the Ovu-FET versus PC-FET groups (62.6% vs. 58.6%, P  = 0.50). Pregnancy rates (77.2% vs. 82.8%, P  = 0.25) and clinical pregnancy rates (69.5% vs. 68.1%, P  = 0.79) were also similar. Clinical loss rates were similar between the two groups (7.0% vs. 9.5%, P  = 0.41). Biochemical loss rates were slightly lower for the Ovu-FET versus PC-FET groups (7.6% vs. 14.7%, P  = 0.06) without reaching statistical significance. Conclusion Our study supports the use of Ovu-FET in women aged 40 years and older undergoing euploid embryo transfers. The results should strengthen confidence in the use of Ovu-FET for older patients.

An important strategy for realizing flexible electronics is to use solution-processable materials that can be directly printed and integrated into high-performance electronic components on plastic. Although examples of functional inks based on metallic, semiconducting and insulating materials have been developed, enhanced printability and performance is still a challenge. Printable high-capacitance dielectrics that serve as gate insulators in organic thin-film transistors are a particular priority. Solid polymer electrolytes (a salt dissolved in a polymer matrix) have been investigated for this purpose, but they suffer from slow polarization response, limiting transistor speed to less than 100 Hz. Here, we demonstrate that an emerging class of polymer electrolytes known as ion gels can serve as printable, high-capacitance gate insulators in organic thin-film transistors. The specific capacitance exceeds that of conventional ceramic or polymeric gate dielectrics, enabling transistor operation at low voltages with kilohertz switching frequencies. Flexible electronics require that all parts can be printed on plastic substrates, but finding materials that can act as high-capacitance dielectrics is a priority. An emerging class of polymer electrolytes, ion gels, can do the job—with high capacitance and at low voltage.

Graphene transistors There is considerable interest in graphene for high-speed electronics applications because of its high carrier mobility, but conventional device-fabrication processes produce significant defects in the atomically thin carbon sheets that constitute graphene, severely degrading device performance. Liao et al . report a novel fabrication approach that circumvents such degradation by placing a nanowire, with a metallic core and insulating shell, on top of the graphene as a gate electrode. 'Source' and 'drain' electrodes are then deposited on graphene through a self-alignment process that causes no appreciable damage to the graphene lattice and preserves its high carrier mobility. This unique device layout ensures that the edges of the source, drain and gate electrodes are positioned precisely, enabling a transistor performance that is comparable in speed with the best existing devices of a similar size. There is much interest in graphene for applications in ultrahigh-speed radio-frequency electronics, but conventional device fabrication processes lead to significant defects in graphene. Here a new way of fabricating high-speed graphene transistors is described. A nanowire with a metallic core and insulating shell is placed as the gate electrode on top of graphene, and source and drain electrodes are deposited through a self-alignment process, causing no appreciable damage to the graphene lattice. Graphene has attracted considerable interest as a potential new electronic material 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 . With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics 12 , 13 , 14 , 15 , 16 , 17 , 18 . However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance 19 , 20 , 21 . Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co 2 Si–Al 2 O 3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm −1 ) and transconductance (1.27 mS μm −1 ) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f T = 100–300 GHz, with the extrinsic f T (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f T of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths 10 .

Printed electronics is a revolutionary technology aimed at unconventional electronic device manufacture on plastic foils, and will probably rely on polymeric semiconductors for organic thin-film transistor (OTFT) fabrication. In addition to having excellent charge-transport characteristics in ambient conditions, such materials must meet other key requirements, such as chemical stability, large solubility in common solvents, and inexpensive solution and/or low-temperature processing. Furthermore, compatibility of both p-channel (hole-transporting) and n-channel (electron-transporting) semiconductors with a single combination of gate dielectric and contact materials is highly desirable to enable powerful complementary circuit technologies, where p- and n-channel OTFTs operate in concert. Polymeric complementary circuits operating in ambient conditions are currently difficult to realize: although excellent p-channel polymers are widely available, the achievement of high-performance n-channel polymers is more challenging. Here we report a highly soluble (∼60 g l -1 ) and printable n-channel polymer exhibiting unprecedented OTFT characteristics (electron mobilities up to ∼0.45–0.85 cm 2  V -1  s -1 ) under ambient conditions in combination with Au contacts and various polymeric dielectrics. Several top-gate OTFTs on plastic substrates were fabricated with the semiconductor-dielectric layers deposited by spin-coating as well as by gravure, flexographic and inkjet printing, demonstrating great processing versatility. Finally, all-printed polymeric complementary inverters (with gain 25–65) have been demonstrated. Printed transistors Printed electronics devices show great potential for cheap consumer and health-care products and new applications are rapidly emerging. But device applications are limited by the fact that the plastic semiconductors currently available are almost exclusively 'hole-transporting' materials that operate via the conduction of positive charges. If an electron-transporting equivalent can be found — retaining good electrical transport properties, chemical stability and ease of processing — then it would be possible to use it in tandem with the existing plastic semiconductors to produce yet more powerful devices. Such combinations are known as 'complementary' circuitry. A team working at the Polyera Corporation labs in the United States and at BASF in Germany has produced a new material that achieves that goal. It is a highly soluble electron-transporting plastic semiconductor that exhibits unprecedented device performance, and is compatible with a broad range of printing and processing technologies. A range of plastic semiconductors have been developed that have the combination of physical and chemical properties required to enable printable electronic circuitry, but these are almost exclusively 'hole transporting' materials. If an electron-transporting equivalent could be found, it could be combined with the existing classes of materials to produce yet more powerful devices. This paper reports the development of a such a material: the electron-transporting plastic semiconductor exhibits unprecedented device performance, and is compatible with a broad range of printing and processing technologies.

Carbon nanotube thin-film transistors 1 are expected to enable the fabrication of high-performance 2 , flexible 3 and transparent 4 devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases) 5 . Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated 6 , 7 , 8 , 9 , 10 , 11 , but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm 2  V –1  s –1 and an on/off ratio of 6 × 10 6 . We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master–slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques. Carbon nanotube transistors with high mobilities and high on/off ratios are demonstrated, along with flexible nanotube-based integrated circuits that are capable of sequential logic.

Carbon nanotube field-effect transistors are strong candidates in replacing or supplementing silicon technology. Although theoretical studies have projected that nanotube transistors will perform well at nanoscale device dimensions 1 , 2 , 3 , 4 , most experimental studies have been carried out on devices that are about ten times larger than current silicon transistors 5 , 6 , 7 . Here, we show that nanotube transistors maintain their performance as their channel length is scaled from 3 µm to 15 nm, with an absence of so-called short-channel effects. The 15-nm device has the shortest channel length and highest room-temperature conductance (0.7 G 0 ) and transconductance (40 µS) of any nanotube transistor reported to date. We also show the first experimental evidence that nanotube device performance depends significantly on contact length, in contrast to some previous reports 8 , 9 , 10 . Data for both channel and contact length scaling were gathered by constructing multiple devices on a single carbon nanotube. Finally, we demonstrate the performance of a nanotube transistor with channel and contact lengths of 20 nm, an on-current of 10 µA, an on/off current ratio of 1 × 10 5 , and peak transconductance of 20 µS. These results provide an experimental forecast for carbon nanotube device performance at dimensions suitable for future transistor technology nodes. Carbon-nanotube transistors exhibit improved performance when their channel length is scaled from 3 μm to 15 nm, and are adversely affected by contact length scaling below 100 nm.

Modeling a stacked-gate core–shell (C-S) junctionless (JL) DG-FET and examining its suitability for low-power applications are the primary focus of the present paper. Here, charge-based analytical 2D modeling is adopted to determine the surface potential, threshold voltage, drain current and drain-induced barrier lowering (DIBL) for various core/shell thickness and shell dopant density values. The analytical model is calibrated with the experimental data available in literature, and the analytical results closely match those obtained from device simulation by Silvaco ATLAS. Next, a comparative analysis is made for C-S-JL-FET, JAM-JL-FET and traditional JL-FET, on the basis of their analog figures of merit (FOMs) [drain current (Id), transconductance generation factor (gm/Id), intrinsic gain (gm/gd), total gate capacitance (Cgg) and Early voltage (VEA)], and linearity FOMs [input power at the third-order intercept point (PIP3), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3) and third-order intermodulation distortion (IMD3)]. The performance of a cascode amplifier is also examined. The entire study reveals that all the gm/Id ratio, VEA and intrinsic gain are largest, along with significantly small OFF-current, for the C-S-JL-FET. It also offers maximum bandwidth with significantly high gain while used in a cascode amplifier. Thus, the C-S-JL-FET appears as a very promising potential candidate for low-power applications.

Organic semiconductors have been the subject of active research for over a decade now, with applications emerging in light-emitting displays and printable electronic circuits. One characteristic feature of these materials is the strong trapping of electrons but not holes 1 : organic field-effect transistors (FETs) typically show p-type, but not n-type, conduction even with the appropriate low-work-function electrodes, except for a few special high-electron-affinity 2 , 3 , 4 or low-bandgap 5 organic semiconductors. Here we demonstrate that the use of an appropriate hydroxyl-free gate dielectric—such as a divinyltetramethylsiloxane-bis(benzocyclobutene) derivative (BCB; ref. 6 )—can yield n-channel FET conduction in most conjugated polymers. The FET electron mobilities thus obtained reveal that electrons are considerably more mobile in these materials than previously thought. Electron mobilities of the order of 10 -3 to 10 -2  cm 2  V -1  s -1 have been measured in a number of polyfluorene copolymers and in a dialkyl-substituted poly( p -phenylenevinylene), all in the unaligned state. We further show that the reason why n-type behaviour has previously been so elusive is the trapping of electrons at the semiconductor–dielectric interface by hydroxyl groups, present in the form of silanols in the case of the commonly used SiO 2 dielectric. These findings should therefore open up new opportunities for organic complementary metal-oxide semiconductor (CMOS) circuits, in which both p-type and n-type behaviours are harnessed.

The efficiency and power density improvement of power switching converters play a crucial role in energy conversion. In the field of motor control, this requires an increase in the converter switching frequency together with a reduction in the switching legs’ dead time. This target turns out to be complex when using pure silicon switch technologies. Gallium Nitride (GaN) devices have appeared in the switching device arena in recent years and feature much more favorable static and dynamic characteristics compared to pure silicon devices. In the field of motion control, there is a growing use of GaN devices, especially in low voltage applications. This paper provides guidelines for designers on the optimal use of GaN FETs in motor control applications, identifying the advantages and discussing the main issues. In this work, primarily an experimental evaluation of GaN FETs in a low voltage electrical drive is carried out. The experimental investigation is obtained through two different experimental boards to highlight the switching legs’ behavior in several operative conditions and different implementations. In this evaluative approach, the main GaN FETs’ technological aspects and issues are recalled and consequently linked to motion control requirements. The device’s fast switching transients combined with reduced direct resistance contribute to decreased power losses. Thus, in GaN FETs, a high switching frequency with a strong decrease in dead time is achievable. The reduced dead time impact on power loss management and improvement of output waveforms quality is analyzed and discussed in this paper. Furthermore, input filter capacitor design matters correlated with increasing switching frequency are pointed out. Finally, the voltage transients slope effect (dv/dt) is considered and correlated with low voltage motor drives requirements.