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"Field programmable gate arrays"
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Jungfraujoch: hardware‐accelerated data‐acquisition system for kilohertz pixel‐array X‐ray detectors
The JUNGFRAU 4‐megapixel (4M) charge‐integrating pixel‐array detector, when operated at a full 2 kHz frame rate, streams data at a rate of 17 GB s−1. To operate this detector for macromolecular crystallography beamlines, a data‐acquisition system called Jungfraujoch was developed. The system, running on a single server with field‐programmable gate arrays and general‐purpose graphics processing units, is capable of handling data produced by the JUNGFRAU 4M detector, including conversion of raw pixel readout to photon counts, compression and on‐the‐fly spot finding. It was also demonstrated that 30 GB s−1 can be handled in performance tests, indicating that the operation of even larger and faster detectors will be achievable in the future. The source code is available from a public repository.
A new data acquisition and real‐time image analysis system with FPGAs and GPUs for kilohertz macromolecular crystallography applications is presented.
Journal Article
Programming FPGAs : getting started with Verilog
\"This fun guide shows how to get started with FPGA technology using the popular Mojo, Papilio One, and Elbert 2 boards. Written by electronics guru Simon Monk, Programming FPGAs: Getting Started with Verilog features clear explanations, easy-to-follow examples, and downloadable sample programs. You'll get start-to-finish assembly and programming instructions for numerous projects, including an LED decoder, a timer, a tone generator - even a memory-mapped video display! The book serves both as a hobbyists' guide and as an introduction for professional developers\"--Publisher's description.
Book
Fractional order systems
This book aims to propose the implementation and application of Fractional Order Systems (FOS). It is well known that FOS can be utilized in control applications and systems modeling, and their effectiveness has been proven in many theoretical works and simulation routines. A further and mandatory step for FOS real world utilization is their hardware implementation and applications on real systems modeling. With this viewpoint, introductory chapters are included on the definition of stability region of Fractional Order PID Controller and Chaotic FOS, followed by the practical implementation based on Microcontroller, Field Programmable Gate Array, Field Programmable Analog Array and Switched Capacitor. Another section is dedicated to FO modeling of Ionic Polymeric Metal Composite (IPMC). This new material will have applications in robotics, aerospace and biomedicine.
eBook
FPGA prototyping by Verilog examples
FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a “learn by doing” approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.
eBook
Learning FPGAs : digital design for beginners with Mojo and Lucid HDL
\"Learn how to design digital circuits with FPGAs (field-programmable gate arrays), the devices that reconfigure themselves to become the very hardware circuits you set out to program. With this practical guide, author Justin Rajewski shows you hands-on how to create FPGA projects, whether you're a programmer, engineer, product designer, or maker. You'll quickly go from the basics to designing your own processor. Designing digital circuits used to be a long and costly endeavor that only big companies could pursue. FPGAs make the process much easier, and now they're affordable enough even for hobbyists. If you're familiar with electricity and basic electrical components, this book starts simply and progresses through increasingly complex projects\"--Publisher's description.
Book
FPGA-Based Processor for Continual Capacitive-Coupling Impedance Spectroscopy and Circuit Parameter Estimation
In principle, the recently proposed capacitive-coupling impedance spectroscopy (CIS) has the capability to acquire frequency spectra of complex electrical impedance sequentially on a millisecond timescale. Even when the measured object with time-varying unknown resistance Rx is capacitively coupled with the measurement electrodes with time-varying unknown capacitance Cx, CIS can be measured. As a proof of concept, this study aimed to develop a prototype that implemented the novel algorithm of CIS and circuit parameter estimation to verify whether the frequency spectra and circuit parameters could be obtained in milliseconds and whether time-varying impedance could be measured. This study proposes a dedicated processor that was implemented as field-programmable gate arrays to perform CIS, estimate Rx and Cx, and their digital-to-analog conversions at a certain time, and to repeat them continually. The proposed processor executed the entire sequence in the order of milliseconds. Combined with a front-end nonsinusoidal oscillator and interfacing circuits, the processor estimated the fixed Rx and fixed Cx with reasonable accuracy. Additionally, the combined system with the processor succeeded in detecting a quick optical response in the resistance of the cadmium sulfide (CdS) photocell connected in series with a capacitor, and in reading out their resistance and capacitance independently as voltages in real-time.
Journal Article
FPGA prototyping by VHDL examples : Xilinx Spartan-3 version
This book uses a \"learn by doing\" approach to introduce the concepts and techniques of VHDL and FPGA to designers through a series of hands-on experiments. FPGA Prototyping by VHDL Examples provides a collection of clear, easy-to-follow templates for quick code development; a large number of practical examples to illustrate and reinforce the concepts and design techniques; realistic projects that can be implemented and tested on a Xilinx prototyping board; and a thorough exploration of the Xilinx PicoBlaze soft-core microcontroller.
eBook
Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia
Aims
The open‐loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real‐time field‐programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC‐specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits.
Methods
We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open‐loop DCN‐DBS or closed‐loop DCN‐DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real‐time computation, was used for closed‐loop DCN‐DBS system.
Results
Closed‐loop DCN‐DBS was triggered only when symptomatic muscle EMG was detected in a real‐time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed‐loop DCN‐DBS was more effective than an open‐loop paradigm as it reduced the frequency of DBS.
Conclusion
Our real‐time FPGA‐based DCN‐DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.
Conventional open‐loop DBS provides continuous stimulation, regardless of changes in physiologic state. Our FPGA‐based closed‐loop DBS system is triggered only when symptomatic muscle EEG is detected in a real‐time manner, which reduced the frequency and time of DBS, preventing over neural stimulation that shortens the battery life of stimulator. The real‐time FPGA‐based closed‐loop DBS system demonstrates a proof‐of‐concept, supporting its potential clinical application in integrating the new generation of implantable pulse generator and external wireless wearable EEG devices for movement disorder.
Journal Article