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Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge₂Sb₂Te₅). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb₂Te₃) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Flash memory has become a ubiquitous solid-state memory device widely used in portable digital devices, computers and enterprise applications. The development of the information age has demanded improvements in memory speed and retention performance. Here we demonstrate an ultrafast non-volatile flash memory based on MoS 2 /hBN/multilayer graphene van der Waals heterostructures, which achieves an ultrafast writing/erasing speed of 20 ns through two-triangle-barrier modified Fowler–Nordheim tunnelling. Using detailed theoretical analysis and experimental verification, we postulate that a suitable barrier height, gate coupling ratio and clean interface are the main reasons for the breakthrough writing/erasing speed of our flash memory devices. Because of its non-volatility this ultrafast flash memory could provide the foundation for the next generation of high-speed non-volatile memory. MoS 2 /hBN/graphene van der Waals heterostructures with a clean interface and optimized barrier height and gate coupling ratio enable the realization of ultrafast non-volatile flash memory.

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances, the authors discuss key design methodologies as well as the various functions and capabilities of the three nonvolatile memory technologies.

In-memory computing could enhance computing energy efficiency by directly implementing multiply accumulate (MAC) operations in a crossbar memory array with low energy consumption (around femtojoules for a single operation). However, a crossbar memory array cannot execute nonlinear activation; moreover, activation processes are power-intensive (around milliwatts), limiting the overall efficiency of in-memory computing. Here we develop an ultrafast bipolar flash memory to execute self-activated MAC operations. Based on atomically sharp van der Waals heterostructures, the basic flash cell has an ultrafast n/p program speed in the range of 20–30 ns and an endurance of 8 × 10 6 cycles. Utilizing sign matching between the input voltage signal and the storage charge type, our bipolar flash can realize a rectified linear unit activation function during the MAC process with a power consumption for each operation of just 30 nW (or 5 fJ of energy). Using a convolutional neural network, we find that the self-activated MAC method has a simulated accuracy of 97.23%, tested on the Modified National Institute of Standards and Technology dataset, which is close to the conventional method where the MAC and activation operations are separated. A flash memory device fabricated with atomically sharp van der Waals heterostructures shows a programming speed of 20–30 ns and power consumption in the nanowatt region.

As the prevailing non-volatile memory (NVM), flash memory offers mass data storage at high integration density and low cost. However, due to the ‘speed-retention-endurance’ dilemma, their typical speed is limited to ~microseconds to milliseconds for program and erase operations, restricting their application in scenarios with high-speed data throughput. Here, by adopting metallic 1T-Li x MoS 2 as edge contact, we show that ultrafast (10–100 ns) and robust (endurance>10 6 cycles, retention>10 years) memory operation can be simultaneously achieved in a two-dimensional van der Waals heterostructure flash memory with 2H-MoS 2 as semiconductor channel. We attribute the superior performance to the gate tunable Schottky barrier at the edge contact, which can facilitate hot carrier injection to the semiconductor channel and subsequent tunneling when compared to a conventional top contact with high density of defects at the metal interface. Our results suggest that contact engineering can become a strategy to further improve the performance of 2D flash memory devices and meet the increasing demands of high speed and reliable data storage. The speed-retention-endurance trade-off usually limits the performance of flash memory devices. Here, the authors report the realization of van der Waals flash memory cells based on 2H-MoS 2 semiconducting channels with phase-engineered 1T-Li x MoS 2 edge contacts, showing program/erasing speed of ~10/100 ns, endurance of >10 6 cycles and expected retention lifetime of >10 years.

Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~ V DD /2), high DC gain exceeding 20 V/V as well as low-voltage operation (< 5 V). The organic flash memory exhibits long retention characteristics (current change less than 10% after 10 4  s), leading to the long-term stability of the 3D T-inverter. We believe the 3D T-inverter employing flash memory developed in this study can provide a useful insight to achieve high-performance MVL circuits. High-density information processing without increasing the circuit complexity is highly desired in electronics. Here, Im et al. demonstrate a low-voltage organic ternary logic circuit vertically integrated with the nonvolatile flash memory, increasing the information density by a factor of 3.

High-current switching performance of ovonic threshold switching (OTS) selectors have successfully enabled the commercialization of high-density three-dimensional (3D) stackable phase-change memory in Intel’s 3D Xpoint technology. This bridges the huge performance gap between dynamic random access memory (DRAM) and Flash. Similar to phase-change memory, OTS uses chalcogenide-based materials, but whereas phase-change memory reversibly switches between a high-resistance amorphous phase and a low-resistance crystalline phase, OTS freezes in the amorphous phase. In this article, we review recent developments in OTS materials and their performance in devices, especially current density and selectivity. Advantages and challenges of OTS devices in the integration with the phase-change memory are discussed. We introduce the evolution of theoretical models for explaining the OTS behavior, including thermal runaway, field-induced nucleation, and generation/recombination of charge carriers.

The adoption of three-dimensional (3D) integration has revolutionized NAND flash memory technology, and a similar transformative potential exists for logic circuits, by stacking transistors into the third dimension. This pivotal shift towards 3D integration of logic arrives on the heels of substantial improvements in silicon device structures and their subsequent scaling in size and performance. Yet, advanced scaling requires ultrathin semiconducting channels, which are difficult to achieve using silicon. In this context, field-effect transistors based on two-dimensional (2D) semiconductors have drawn notable attention owing to their atomically thin nature and impressive performance milestones. In addition, 2D materials offer a broader spectrum of functionalities — such as optical, chemical and biological sensing — that extends their utility beyond simple ‘more Moore’ dimensional scaling and enables the development of ‘more than Moore’ technologies. Thus, 3D integration of 2D electronics could bring us unanticipated discoveries, leading to sustainable and energy-efficient computing systems. In this Review, we explore the progress, challenges and future opportunities for 3D integration of 2D electronics.Since the most advanced nodes in silicon are reaching the limits of planar integration, 2D materials could help to advance the semiconductor industry. With the potential for use in multifunctional chips, 2D materials offer combined logic, memory and sensing in integrated 3D chips.

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.