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"Gate arrays"
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DNA-based programmable gate arrays for general-purpose DNA computing
The past decades have witnessed the evolution of electronic and photonic integrated circuits, from application specific to programmable
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. Although liquid-phase DNA circuitry holds the potential for massive parallelism in the encoding and execution of algorithms
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, the development of general-purpose DNA integrated circuits (DICs) has yet to be explored. Here we demonstrate a DIC system by integration of multilayer DNA-based programmable gate arrays (DPGAs). We find that the use of generic single-stranded oligonucleotides as a uniform transmission signal can reliably integrate large-scale DICs with minimal leakage and high fidelity for general-purpose computing. Reconfiguration of a single DPGA with 24 addressable dual-rail gates can be programmed with wiring instructions to implement over 100 billion distinct circuits. Furthermore, to control the intrinsically random collision of molecules, we designed DNA origami registers to provide the directionality for asynchronous execution of cascaded DPGAs. We exemplify this by a quadratic equation-solving DIC assembled with three layers of cascade DPGAs comprising 30 logic gates with around 500 DNA strands. We further show that integration of a DPGA with an analog-to-digital converter can classify disease-related microRNAs. The ability to integrate large-scale DPGA networks without apparent signal attenuation marks a key step towards general-purpose DNA computing.
Generic single-stranded oligonucleotides used as a uniform transmission signal can reliably integrate large-scale DNA integrated circuits with minimal leakage and high fidelity for general-purpose computing.
Journal Article
Programming FPGAs : getting started with Verilog
\"This fun guide shows how to get started with FPGA technology using the popular Mojo, Papilio One, and Elbert 2 boards. Written by electronics guru Simon Monk, Programming FPGAs: Getting Started with Verilog features clear explanations, easy-to-follow examples, and downloadable sample programs. You'll get start-to-finish assembly and programming instructions for numerous projects, including an LED decoder, a timer, a tone generator - even a memory-mapped video display! The book serves both as a hobbyists' guide and as an introduction for professional developers\"--Publisher's description.
Book
Jungfraujoch: hardware‐accelerated data‐acquisition system for kilohertz pixel‐array X‐ray detectors
The JUNGFRAU 4‐megapixel (4M) charge‐integrating pixel‐array detector, when operated at a full 2 kHz frame rate, streams data at a rate of 17 GB s−1. To operate this detector for macromolecular crystallography beamlines, a data‐acquisition system called Jungfraujoch was developed. The system, running on a single server with field‐programmable gate arrays and general‐purpose graphics processing units, is capable of handling data produced by the JUNGFRAU 4M detector, including conversion of raw pixel readout to photon counts, compression and on‐the‐fly spot finding. It was also demonstrated that 30 GB s−1 can be handled in performance tests, indicating that the operation of even larger and faster detectors will be achievable in the future. The source code is available from a public repository. A new data acquisition and real‐time image analysis system with FPGAs and GPUs for kilohertz macromolecular crystallography applications is presented.
Journal Article
Ten years of hardware Trojans: a survey from the attacker's perspective
Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property vendor attacks, computer-aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field-programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti-detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.
Journal Article
Learning FPGAs : digital design for beginners with Mojo and Lucid HDL
\"Learn how to design digital circuits with FPGAs (field-programmable gate arrays), the devices that reconfigure themselves to become the very hardware circuits you set out to program. With this practical guide, author Justin Rajewski shows you hands-on how to create FPGA projects, whether you're a programmer, engineer, product designer, or maker. You'll quickly go from the basics to designing your own processor. Designing digital circuits used to be a long and costly endeavor that only big companies could pursue. FPGAs make the process much easier, and now they're affordable enough even for hobbyists. If you're familiar with electricity and basic electrical components, this book starts simply and progresses through increasingly complex projects\"--Publisher's description.
Book
In situ quality control of the selective laser melting process using a high-speed, real-time melt pool monitoring system
This paper discusses the principle and the relevance of an in situ monitoring system for selective laser melting (SLM). This system enables the operator to monitor the quality of the SLM job on-line and estimate the quality of the part accordingly. The monitoring system consists of two major developments in hardware and software. The first development, essential for a suitable monitoring system, is the design of a complete optical sensor set-up. This set-up is equipped with two commercially available optical sensors connected to a field-programmable gate array (FPGA) which communicates directly with the machine control unit. While the sensors ensure a high-quality measurement of the melt pool, the FPGA’s main task is to transfer the images from the sensors into relevant values at high sample rates (above 10 kHz). The second development is the data analysis system to translate and visualize measured sensor values in the format of interpretable process quality images. The visualization is mainly done by a “mapping algorithm,” which transfers the measurements from a time-domain into a position-domain representation. Further off-line experiments illustrate an excellent compatibility between the in situ monitoring and the actual quality of the products. The resulting images coming out of this model illustrate melt pool variations which can be linked to pores that are present in the parts.
Journal Article
Design for Embedded Image Processing on FPGAs
Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned. <ul type=\"disc\"> <li>Provides a bridge between algorithms and hardware</li> <li>Demonstrates how to avoid many of the potential pitfalls</li> <li>Offers practical recommendations and solutions</li> <li>Illustrates several real-world applications and case studies</li> <li>Allows those with software backgrounds to understand efficient hardware implementation</li> </ul> <p><i>Design for Embedded Image Processing on FPGAs</i> is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.</p> <p>The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.</p> <p>Lecture slides for instructors available at:</p> <p>www.wiley.com/go/bailey/fpga</p>
eBook
FPGA‐accelerated streaming data reduction achieving an average compression ratio over 8000 in a 17.4 kHz, 840 kpixel CITIUS detector for quasi‐elastic gamma‐ray scattering
We present a data‐acquisition and ‐analysis framework for quasi‐elastic gamma‐ray scattering (QEGS) experiments at BL35XU of SPring‐8, equipped with an 840 kpixel CITIUS X‐ray detector operating at 17.4 kHz. The detector produces data at 27 GB s−1 (216 Gbps), and typical experiments involve acquisition over beam‐time periods longer than 24 h, generating datasets of 2.3 PB per day. To handle this volume, we constructed a data‐handling pipeline consisting of the detector, data reduction at the beamline and analysis tools at the data center. The data reduction employs field‐programmable gate array (FPGA)‐accelerated per‐pixel processing to reduce data entropy, followed by Zstandard compression on CPUs, achieving an average compression ratio of over 8000. The compressed data are transferred to the SPring‐8 data center within two to three minutes of data acquisition. At the data center, analysis tools are provided via the Open OnDemand platform, enabling incremental integration and spectral analysis through a web‐based interface without the need for high‐performance‐computing command‐line interaction. This data‐handling pipeline has been applied in QEGS user experiments, where it enabled timely feedback on experimental data, with integrated results available within six minutes and spectral analysis within seven minutes of integration. A high‐throughput field‐programmable gate array (FPGA)‐accelerated data‐reduction and ‐analysis pipeline combined with high‐performance computing enables the continuous handling of a 216 Gbps data stream from quasi‐elastic gamma‐ray scattering experiments at SPring‐8.
Journal Article