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Multipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hardware resources, particularly in applications where that can tolerate minimal accuracy loss. Achieving higher multiplier performance typically requires a careful trade-off between hardware complexity and computational precision. One widely adopted method for designing approximate multipliers involves replacing exact compressors with their approximate counterparts, resulting in a trade-off with accuracy. This paper introduces novel approximate multiplier architectures that partition the computation into three distinct regions: accurate, approximate, and lower region. Partial product compression in the approximate region is carried out using the proposed two 4:2 compressors combined with conventional arithmetic circuits like half adder, full adder and OR logic, to produce the final product. The proposed compressors are developed by analyzing the input occurrence probability of all possible combinations with trade-off between hardware efficiency and computational accuracy. To further improve accuracy, an error correction logic is developed to compensate for inaccuracies in specific input scenarios. Several benchmark error metrics and hardware synthesis using a 32-nm CMOS technology are evaluated for the proposed designs through simulations. Notably, the results of the proposed approximate multipliers shows an average improvements of 70.6% in accuracy, 60.4% in Energy-Delay Product, 30.9% in Power-Delay Product, and 41.6% in delay, outperforming all existing designs considered for comparison. Furthermore, real-time image multiplication experiments were performed using multiple benchmark image datasets, and the output quality was evaluated through the Similarity Index Metric (SSIM) and Peak Signal-to-Noise Ratio (PSNR). In addition, detailed error and heat-map visual analyses were conducted to examine the spatial distribution and intensity of computational errors across pixels. The results demonstrate that the proposed multiplier consistently achieves higher SSIM and PSNR values, along with significantly reduced error concentrations, outperforming existing approximate multiplier designs.

The resolution of aerial images was low, because the aviation aerospace camera was far from the scenery when shooting. In order to see the object of the aviation images clearly,the aviation images should be enlarged to improve the resolution . As the complexity and irregularity of the aerial images, the texture features is lost and considerable error is caused by using the traditional methods. In this article, the fractal interpolation has been used to enlarge the images, which can not only overcome the shortcoming of the linear interpolation, but also maintain the fine texture features of the original images, which is helpful to obtain higher accuracy than the traditional interpolation.

This chapter contains sections titled: Introduction Arithmetic Operations Empirically Based Image Transforms Principal Components Analysis Hue‐Saturation‐Intensity (HSI) Transform The Discrete Fourier Transform The Discrete Wavelet Transform Change Detection Image Fusion Summary

This chapter considers the four basic arithmetic operations: addition, subtraction, multiplication and division. In multi‐image point operations, arithmetic processing is sometimes the same as matrix operations, such as addition and subtraction, but sometimes totally different from and much simpler than matrix operations, such as image multiplication and division. Infinite combinations of algebraic operations can be derived from basic arithmetic operations and algebraic functions. An index can be considered as supervised enhancement. The chapter introduces a few commonly used examples of indices based on Landsat TM/ETM+ image data. We may design our own indices for a given image processing task based on spectral analysis. Many image processing techniques have been developed on the basis of fairly sophisticated physical or mathematical models, but the actual constituent operations are simple arithmetic operations. One important issue for spectral enhancement is the suppression of topographic shadowing effects.

Semantic scene completion (SSC) aims to jointly estimate the complete geometry and semantics of a scene, assuming partial sparse input. In the last years following the multiplication of large-scale 3D datasets, SSC has gained significant momentum in the research community because it holds unresolved challenges. Specifically, SSC lies in the ambiguous completion of large unobserved areas and the weak supervision signal of the ground truth. This led to a substantially increasing number of papers on the matter. This survey aims to identify, compare and analyze the techniques providing a critical analysis of the SSC literature on both methods and datasets. Throughout the paper, we provide an in-depth analysis of the existing works covering all choices made by the authors while highlighting the remaining avenues of research. SSC performance of the SoA on the most popular datasets is also evaluated and analyzed.

Neuromorphic photonics has recently emerged as a promising hardware accelerator, with significant potential speed and energy advantages over digital electronics for machine learning algorithms, such as neural networks of various types. Integrated photonic networks are particularly powerful in performing analog computing of matrix-vector multiplication (MVM) as they afford unparalleled speed and bandwidth density for data transmission. Incorporating nonvolatile phase-change materials in integrated photonic devices enables indispensable programming and in-memory computing capabilities for on-chip optical computing. Here, we demonstrate a multimode photonic computing core consisting of an array of programable mode converters based on on-waveguide metasurfaces made of phase-change materials. The programmable converters utilize the refractive index change of the phase-change material Ge 2 Sb 2 Te 5 during phase transition to control the waveguide spatial modes with a very high precision of up to 64 levels in modal contrast. This contrast is used to represent the matrix elements, with 6-bit resolution and both positive and negative values, to perform MVM computation in neural network algorithms. We demonstrate a prototypical optical convolutional neural network that can perform image processing and recognition tasks with high accuracy. With a broad operation bandwidth and a compact device footprint, the demonstrated multimode photonic core is promising toward large-scale photonic neural networks with ultrahigh computation throughputs. Integrated optical computing requires programmable photonic and nonlinear elements. The authors demonstrate a phase-change metasurface mode converter, which can be programmed to control the waveguide mode contrast, and build an optical convolutional neural network to perform image processing tasks.

A new super-resolution (SR) technique by CNNs is introduced: Lightweight Duplication Super Resolution Network (LDPSR). This network achieves performance similar to mainstream non-lightweight network networks while maintaining a lower calculation cost and number of parameters, and has specially designed a Lightweight Duplication Plugin (LDP), which only generates addition operations without increasing the burden of multiplication operations, effectively improving the computational performance of the network. This plugin greatly reduces the network size by segmenting input images and expanding them separately to avoid increasing the parameter count. The network architecture includes a shallow part, a deep part, and an up-sampling part. By combining special convolution modules and lightweight plugins, the diversity of features is enhanced while controlling the parameters and costs of computational. This study provides a new network architecture and computing method that can achieve efficient SR on lightweight devices with lower computational costs and parameter requirements, to achieve the practical application value of SR technology.

Deep learning has become a widespread tool in both science and industry. However, continued progress is hampered by the rapid growth in energy costs of ever-larger deep neural networks. Optical neural networks provide a potential means to solve the energy-cost problem faced by deep learning. Here, we experimentally demonstrate an optical neural network based on optical dot products that achieves 99% accuracy on handwritten-digit classification using ~3.1 detected photons per weight multiplication and ~90% accuracy using ~0.66 photons (~2.5 × 10 −19  J of optical energy) per weight multiplication. The fundamental principle enabling our sub-photon-per-multiplication demonstration—noise reduction from the accumulation of scalar multiplications in dot-product sums—is applicable to many different optical-neural-network architectures. Our work shows that optical neural networks can achieve accurate results using extremely low optical energies. Though theory suggests that highly energy efficient optical neural networks (ONNs) based on optical matrix-vector multipliers are possible, an experimental validation is lacking. Here, the authors report an ONN with >90% accuracy image classification using <1 detected photon per scalar multiplication.

Memristor crossbars offer reconfigurable non-volatile resistance states and could remove the speed and energy efficiency bottleneck in vector-matrix multiplication, a core computing task in signal and image processing. Using such systems to multiply an analogue-voltage-amplitude-vector by an analogue-conductance-matrix at a reasonably large scale has, however, proved challenging due to difficulties in device engineering and array integration. Here we show that reconfigurable memristor crossbars composed of hafnium oxide memristors on top of metal-oxide-semiconductor transistors are capable of analogue vector-matrix multiplication with array sizes of up to 128 × 64 cells. Our output precision (5–8 bits, depending on the array size) is the result of high device yield (99.8%) and the multilevel, stable states of the memristors, while the linear device current–voltage characteristics and low wire resistance between cells leads to high accuracy. With the large memristor crossbars, we demonstrate signal processing, image compression and convolutional filtering, which are expected to be important applications in the development of the Internet of Things (IoT) and edge computing. Main Memristor crossbars with array sizes of up to 128 × 64 cells are capable of analogue vector-matrix multiplication and can be used for signal processing, image compression and convolutional filtering.

Toom-Cook multiplication algorithm is one of the most efficient method compared to other traditional large-integer multiplication algorithms. However, in most cases, implementation of this algorithm in hardware is practically avoided due to presence of exact-divisions at intermediate steps of computation. Thus this paper proposes ways to overcome the limitation by designing a hardware-optimized, division-free Toom-4 multiplication algorithm. This is done by eliminating the effects of division due to odd factors in the denominator using a scaling factor, at the interpolation step of the algorithm. Further optimization is done by replacing the direct point-wise multiplication with an optimized Schoolbook multiplication. The overall performance of the proposed architecture is estimated using Area-Time-Product (ATP) and hardware implementation is done using Virtex-7 FPGA device in Xilinx-ISE platform. Practically, the proposed design performs better in terms of speed and resource utilization for higher input bits compared to other state-of-the-art designs; for example for 512 input bits, the percentage ATP of the proposed design is 75.077%, 98.822% and 57.316% superior performance compared to Traditional Schoolbook Multiplication, Karatsuba (Toom-2) multiplication and Toom-4 multiplication respectively.