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VLSI Test Principles and Architectures - Design for Testability
This book is a comprehensive guide to new design for testability (DFT) methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Key features include up-to-date coverage of design for testability, coverage of industry practices commonly found in commercial DFT tools but not discussed in other books, and numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Practitioners/Researchers in VLSI design and testing; design or test engineers, as well as research institutes will benefit from this book. This book is also appropriate for undergraduate and graduate-level courses in electronic testing, digital systems testing, digital logic test and simulation, and VLSI design.
eBook
A 5 GS/s Highly Linear Voltage‐Scalable Voltage‐to‐Time Converter for Time Domain ADCs
A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals. The proposed VTC is designed in the 28 nm CMOS process, occupying an area of 972 μm2 $\\mu{\\rm m}^2$ . Post‐layout simulation results demonstrate that, with an input voltage of 1.4 Vpp,diff ${\\rm V}_{\\text{pp}, \\text{diff}}$ , the VTC achieves a total harmonic distortion (THD) of −62.9 dB and a spurious‐free dynamic range (SFDR) of 65.5 dB for Nyquist input, while consuming only 1.92 mW of power. A novel 5 GS/s highly linear voltage‐scalable voltage‐to‐time converter (VTC) has been presented for the time‐domain (TD) ADCs. The proposed VTC employs an innovative sample‐and‐hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade‐off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high‐frequency input signals.
Journal Article
Microelectronic circuits
CD-ROM contains: free student version of PSpice 9.2 Lite Edition (SPICE simulator) and new industry-based design examples.
Book
The Medium Energy X-ray telescope (ME) onboard the Insight-HXMT astronomy satellite
The Medium Energy X-ray telescope (ME) is one of the three main telescopes on board the
Insight
hard X-ray modulation telescope (
Insight-
HXMT) astronomy satellite. ME contains 1728 pixels of Si-PIN detectors sensitive in 5–30 keV with a total geometrical area of 952 cm
2
. The application specific integrated circuit (ASIC) chip, VA32TA6, is used to achieve low power consumption and low readout noise. The collimators define three kinds of field of views (FOVs) for the telescope, 1°×4°, 4°×4°, and blocked ones. Combination of such FOVs can be used to estimate the in-orbit X-ray and particle background components. The energy resolution of ME is ~3 keV at 17.8 keV (FWHM) and the time resolution is 255 μs. In this paper, we introduce the design and performance of ME.
Journal Article
Modern semiconductor devices for integrated circuits
'Modern Semiconductor Devices for Integrated Circuits' introduces students to the world of modern semiconductor devices with an emphasis on integrated circuit applications.
ReCIM: A SRAM‐Based Digital–Analogue Hybrid CIM Reformer Accelerator Macro
Reformer reduces redundant self‐attention computations via hash bucketing. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory (ReCIM) accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Additionally, we introduce a reusable weight array which is suitable for matrix operations across various processes of self‐attention, minimising unnecessary area overhead and enhancing device reusability. The proposed 4 Kb ReCIM macro was analysed using 28‐nm CMOS technology. Simulation results demonstrate that the macro achieves a frequency of 500 MHz at a supply voltage of 0.9 V. During the hash bucketing process, energy efficiency reaches 9.74 TOPS/W. In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving computational efficiency and saving memory space. Simulation results show that the data processing frequency for implementing hash bucketing is as high as 500 MHz, and the energy efficiency is 9.74 TOPS/W.
Journal Article
A 0.8–3.2 GHz Fast‐Lock Duty‐Cycle Corrector for NAND Flash Interfaces With 50% Lower SAR‐Induced Duty‐Quantisation Error
This paper presents a wide‐range, fast‐lock duty‐cycle corrector (DCC) with a 5‐bit successive‐approximation register (SAR). An inverter‐based bang‐bang duty‐cycle detector (BBDCD) is equalised before each comparison to suppress hysteresis, enabling deterministic decisions and a fixed 4‐cycle per‐bit schedule. The duty‐cycle adjuster (DCA) uses a controller frequency code for range adjustment and applies delay equalisation to limit code‐dependent delay during updates. A half‐LSB post‐bias then halves the SAR quantisation‐error bound without extra cycles. Post‐layout simulations in 28‐nm CMOS show operation from 0.8 to 3.2 GHz over 38%–62% input duty with a 20‐cycle lock, ≤1.0% maximum duty error, and 1.73 mW at 3.2 GHz. This letter presents a wide‐range, fast‐lock DCC for NAND Flash interfaces using an inverter‐based equalised BBDCD and 5‐bit SAR control. A half‐LSB post‐bias halves the quantisation‐error bound while maintaining ≤1% duty error and 1.73 mW power at 3.2 GHz in 28‐nm CMOS.
Journal Article