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This book is a comprehensive guide to new design for testability (DFT) methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Key features include up-to-date coverage of design for testability, coverage of industry practices commonly found in commercial DFT tools but not discussed in other books, and numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Practitioners/Researchers in VLSI design and testing; design or test engineers, as well as research institutes will benefit from this book. This book is also appropriate for undergraduate and graduate-level courses in electronic testing, digital systems testing, digital logic test and simulation, and VLSI design.

An expert guide to the new and emerging field of broadband circuits for optical fiber communication This exciting publication makes it easy for readers to enter into and deepen their knowledge of the new and emerging field of broadband circuits for optical fiber communication. The author's selection and organization of material have been developed, tested, and refined from his many industry courses and seminars. Five types of broadband circuits are discussed in detail: * Transimpedance amplifiers * Limiting amplifiers * Automatic gain control (AGC) amplifiers * Lasers drivers * Modulator drivers Essential background on optical fiber, photodetectors, lasers, modulators, and receiver theory is presented to help readers understand the system environment in which these broadband circuits operate. For each circuit type, the main specifications and their impact on system performance are explained and illustrated with numerical values. Next, the circuit concepts are discussed and illustrated with practical implementations. A broad range of circuits in MESFET, HFET, BJT, HBT, BiCMOS, and CMOS technologies is covered. Emphasis is on circuits for digital, continuous-mode transmission in the 2.5 to 40 Gb/s range, typically used in SONET, SDH, and Gigabit Ethernet applications. Burst-mode circuits for passive optical networks (PON) and analog circuits for hybrid fiber-coax (HFC) cable-TV applications also are discussed. Learning aids are provided throughout the text to help readers grasp and apply difficult concepts and techniques, including: * Chapter summaries that highlight the key points * Problem-and-answer sections to help readers apply their new knowledge * Research directions that point to exciting new technological breakthroughs on the horizon * Product examples that show the performance of actual broadband circuits * Appendices that cover eye diagrams, differential circuits, S parameters, transistors, and technologies * A bibliography that leads readers to more complete and in-depth treatment of specialized topics This is a superior learning tool for upper-level undergraduates and graduate-level students in circuit design and optical fiber communication. Unlike other texts that concentrate on analog circuits in general or mostly on optics, this text provides balanced coverage of electronic, optic, and system issues. Professionals in the fiber optic industry will find it an excellent reference, incorporating the latest technology and discoveries in the industry.

Carbon nanotube field-effect transistors (CNTFETs) are increasingly recognized as a viable option for creating high-performance, low-power, and densely integrated circuits (ICs). Advancements in carbon-based electronics, encompassing materials and device technology, have enabled the fabrication of circuits with over 1000 gates, marking carbon-based integrated circuit design as a burgeoning field of research. A critical challenge in the realm of carbon-based very-large-scale integration (VLSI) is the lack of suitable automated design methodologies and infrastructure platforms. In this study, we present the development of a wafer-scale 3 µm carbon-based complementary metal-oxide-semiconductor (CMOS) process design kit (PDK) (3 µm-CNTFETs-PDK) compatible with silicon-based Electronic Design Automation (EDA) tools and VLSI circuit design flow. The proposed 3 µm-CNTFETs-PDK features a contacted gate pitch (CGP) of 21 µm, a gate density of 128 gates/mm 2 , and a transistor density of 554 transistors/mm 2 , with an intrinsic gate delay around 134 ns. Validation of the 3 µm-CNTFETs-PDK was achieved through the successful design and tape-out of 153 standard cells and 333-stage ring oscillator circuits. Leveraging the carbon-based PDK and a silicon-based design platform, we successfully implemented a complete 64-bit static random-access memory (SRAM) circuit system for the first time, which exhibited timing, power, and area characteristics of clock@10 kHz, 122.1 µW, 3795 µm × 2810 µm. This research confirms that carbon-based IC design can be compatible with existing EDA tools and silicon-based VLSI design flow, thereby laying the groundwork for future carbon-based VLSI advancements.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI testing and design-for-testability (DFT) techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly system-on-chip test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast and accurate parasitic capacitance extraction is therefore essential in the back-end-of-line (BEOL) stage. Currently, 2.5D parasitic capacitance extraction flow based on the pattern matching method is widely used by commercial tools, which still suffer from lengthy pattern library construction, cross-section preprocessing, pattern mismatch, and poor accuracy for small capacitance extraction. To overcome these limitations, this work proposes an end-to-end parasitic capacitance extraction workflow, named residual multilayer perceptron interconnect parasitic capacitance extraction (RMLP-Cap), which leverages a residual multilayer perceptron (ResMLP) to enhance traditional workflow. RMLP-Cap integrates parasitic extraction (PEX) window acquisition, pattern definition, feature extraction, dataset generation, ResMLP model training, and capacitance aggregation into a unified flow. Experimental results show that RMLP-Cap can automatically define and model complex 2D patterns with 100% matching accuracy. Compared with a field solver based on the boundary element method (BEM), the ResMLP model achieves an average relative error below 0.9%, a standard deviation under 0.2%, and less than 0.5% error for small capacitances, while providing a 900% speed improvement for extraction speed.

Graphs have provided an expressive mathematical tool to model quantum-mechanical devices and systems. In particular, it has been recently discovered that graph theory can be used to describe and design quantum components, devices, setups and systems, based on the two-dimensional lattice of parametric nonlinear optical crystals and linear optical circuits, different to the standard quantum photonic framework. Realizing such graph-theoretical quantum photonic hardware, however, remains extremely challenging experimentally using conventional technologies. Here we demonstrate a graph-theoretical programmable quantum photonic device in very-large-scale integrated nanophotonic circuits. The device monolithically integrates about 2,500 components, constructing a synthetic lattice of nonlinear photon-pair waveguide sources and linear optical waveguide circuits, and it is fabricated on an eight-inch silicon-on-insulator wafer by complementary metal–oxide–semiconductor processes. We reconfigure the quantum device to realize and process complex-weighted graphs with different topologies and to implement different tasks associated with the perfect matching property of graphs. As two non-trivial examples, we show the generation of genuine multipartite multidimensional quantum entanglement with different entanglement structures, and the measurement of probability distributions proportional to the modulus-squared hafnian (permanent) of the graph’s adjacency matrices. This work realizes a prototype of graph-theoretical quantum photonic devices manufactured by very-large-scale integration technologies, featuring arbitrary programmability, high architectural modularity and massive manufacturing scalability.A graph-theoretical programmable quantum photonic device composed of about 2,500 components is fabricated on a silicon substrate within a 12 mm × 15 mm footprint. It shows the generation, manipulation and certification of genuine multiphoton multidimensional entanglement, as well as the implementations of scattershot and Gaussian boson sampling.

With advancements in remote sensing technology and very-large-scale integration (VLSI) circuit technology, the Earth observation capabilities of spaceborne synthetic aperture radar (SAR) have continuously improved, leading to significantly increased performance demands for on-board SAR real-time imaging processors. Currently, the low data access efficiency of traditional direct memory access (DMA) engines remains a critical technical bottleneck limiting the real-time processing performance of SAR imaging systems. To address this limitation, this paper proposes a dedicated instruction set for spaceborne SAR data transfer control, leveraging the memory access characteristics of DDR4 SDRAM and common data read/write address jump patterns during on-board SAR real-time imaging processing. This instruction set can significantly reduce the number of instructions required in DMA engine data access operations and optimize data access logic patterns. While effectively reducing memory resource usage, it also substantially enhances the data access efficiency of DMA engines. Based on the proposed dedicated instruction set, we designed a DMA engine optimized for efficient data access in on-board SAR real-time imaging processing scenarios. Module-level performance tests were conducted on this engine, and full-process imaging experiments were performed using an FPGA-based SAR imaging system. Experimental results demonstrate that, under spaceborne SAR imaging processing conditions, the proposed DMA engine achieves a receive data bandwidth of 2.385 GB/s and a transmit data bandwidth of 2.649 GB/s at a 200 MHz clock frequency, indicating excellent memory access bandwidth and efficiency. Furthermore, tests show that the complete SAR imaging system incorporating this DMA engine processes a 16 k × 16 k SAR image using the Chirp Scaling (CS) algorithm in 1.2325 s, representing a significant improvement in timeliness compared to existing solutions.

A reprint of the classic text, this book popularized compact modeling of electronic and semiconductor devices and components for college and graduate-school classrooms, and manufacturing engineering, over a decade ago. The first comprehensive book on MOS transistor compact modeling, it was the most cited among similar books in the area and remains the most frequently cited today. The coverage is device-physics based and continues to be relevant to the latest advances in MOS transistor modeling. This is also the only book that discusses in detail how to measure device model parameters required for circuit simulations.

As chip interconnect density increases, routing problems become increasingly complex. The routing scheme significantly impacts key performance indicators such as chip delay, power consumption, and area. In Very Large-Scale Integration (VLSI) routing, the rectilinear Steiner minimal tree is an excellent interconnect model for multi-pin nets. However, modern VLSI designs require multi-layer obstacle-avoiding routing, where wires must traverse multiple metal layers while avoiding obstacles to ensure connectivity and performance. This makes the Multi-Layer Obstacle-Avoiding Rectilinear Steiner Minimal Tree (ML-OARSMT) problem highly challenging in VLSI physical design. To address this issue, this paper proposes an ML-OARSMT construction algorithm based on deep reinforcement learning. First, a multi-layer obstacle-avoiding spanning graph is constructed by introducing vertex mapping, which connects different layers to handle the multi-layer obstacle-avoiding routing problem. Then, an agent is designed to learn edge selection for constructing the Multi-Layer Obstacle-Avoiding Steiner Tree (ML-OAST) using Double Deep Q-Network (DDQN). Finally, a post-processing stage is applied to further shorten the total wirelength through fast pruning and local optimization. Experimental results demonstrate that the proposed algorithm achieves better wirelength quality compared to state-of-the-art heuristic algorithms. Additionally, an ablation study confirms the effectiveness of DDQN in routing optimization.

Full adder is one of the important components in electronics, used for various fundamental processing algorithms such as addition and multiplication. The application of these full adders is included in but not limited to Very Large-Scale Integration (VLSI) and Digital Signal Processing (DSP). To provide scalability and reliability to the advanced algorithms for high-end applications, the designing system of full adder should be enhanced. So, in this paper, we intended to improve the efficiency of a full adder circuit to work under low power and delay conditions. The software we used in this project is MENTOR GRAPHICS using 180 nm technology. The efficiency of the proposed transistor design is evaluated by analysing the power consumption, delay, PDP, capacitor load, delay w.r.t capacitance and PDP w.r.t capacitance. The parameters are compared between our proposed design and the literature schemes such as OLPFAD, DFEFA, DTLPCFA, and DPEHFA, respectively. It is evident that our proposed design outperforms the other.