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With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage 1 . This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2  (ref.  2 ), which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current 3 . Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials. In the standard Si transistor gate stack, replacing conventional dielectric HfO 2  with an ultrathin ferroelectric–antiferroelectric HfO 2 –ZrO 2  heterostructure exhibiting the negative capacitance effect demonstrates ultrahigh capacitance without degradation in leakage and mobility, promising for ferroelectric integration into advanced logic technology.

Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors 1 – 4 . However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties 3 , 5 , 6 . Here we demonstrate the fabrication of atomically thin single-crystalline Al 2 O 3 (c-Al 2 O 3 ) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al 2 O 3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al 2 O 3 meet the International Roadmap for Devices and Systems requirements 3 , 5 , 7 . Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS 2 FETs characterized by a steep subthreshold swing of 61 mV dec −1 , high on/off current ratio of 10 8 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors. By using intercalative oxidation techniques, stable, stoichiometric and atomically thin single-crystalline Al 2 O 3 films can be produced, which can be effectively used as a dielectric in top-gated field-effect transistors based on two-dimensional materials.

Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in miniaturized integrated circuits. However, the 2D dielectrics explored to date still face the challenges of low crystallinity, diminished dielectric constant, and the lack of effective synthesis methods. Here, we report the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrate-assisted chemical vapor deposition (CVD) method. The resultant GdOCl nanosheets display good dielectric properties, including a high dielectric constant (high-κ) of 15.3, robust breakdown field strengths ( E bd ) exceeding 9.9 MV/cm, and minimal gate leakage currents of approximately 10 −6 A/cm 2 . The top-gated GdOCl/MoS 2 field-effect transistors (FETs) exhibit commendable switch characteristics, a negligible hysteresis of ~5 mV and a subthreshold swing down to 67.9 mV dec −1 . The GdOCl/MoS 2 FETs can also be employed to construct functional logic gates. Our study underscores the significant potential of the 2D GdOCl dielectric for innovative high-speed operated nanoelectronic devices. van der Waals dielectric materials are required to promote the industrialization of miniaturized 2D electronics. Here, the authors report the growth of GdOCl single crystals with a dielectric constant of 15.3 and equivalent oxide thickness down to 1.3 nm, showing their application for the realization of high-performance 2D MoS 2 transistors.

This work employed pulse scanning techniques to systematically investigate the hysteresis characteristics of top-gated array CNT FETs. Based on the trap capture mechanism, it explained the hysteretic nature of the non-coinciding electrical characteristic curves during positive and negative scans. By adjusting the scanning range and pulse width, it was further verified that trap capture is the core mechanism inducing device hysteresis. Concurrently, this work investigated the conduction mechanisms of gate leakage current (IG) in the device. Research findings indicate that the dominant conduction mechanism of gate leakage current exhibits significant dependence on the gate voltage range. Within specific gate voltage intervals, leakage mechanisms closely coupled with trap behavior exist within the system, with space-charge-limited current (SCL) being a typical example.

Two-dimensional semiconductors could be used as a channel material in low-power transistors, but the deposition of high-quality, ultrathin high- κ dielectrics on such materials has proved challenging. In particular, atomic layer deposition typically leads to non-uniform nucleation and island formation, creating a porous dielectric layer that suffers from current leakage, particularly when the equivalent oxide thickness is small. Here, we report the atomic layer deposition of high- κ gate dielectrics on two-dimensional semiconductors using a monolayer molecular crystal as a seeding layer. The approach can be used to grow dielectrics with an equivalent oxide thickness of 1 nm on graphene, molybdenum disulfide (MoS 2 ) and tungsten diselenide (WSe 2 ). Compared with dielectrics created using established methods, our dielectrics exhibit a reduced roughness, density of interface states and leakage current, as well as an improved breakdown field. With the technique, we fabricate graphene radio-frequency transistors that operate at 60 GHz, and MoS 2 and WSe 2 complementary metal–oxide–semiconductor transistors with a supply voltage of 0.8 V and subthreshold swing down to 60 mV dec −1 . We also create MoS 2 transistors with a channel length of 20 nm, which exhibit an on/off ratio of over 10 7 . Using a monolayer molecular crystal as a seeding layer, hafnium oxide dielectrics with an equivalent oxide thickness of only 1 nm can be deposited on graphene, molybdenum disulfide and tungsten diselenide.

Two-dimensional semiconductors could be used to fabricate ultimately scaled field-effect transistors and more-than-Moore nanoelectronic devices. However, these targets cannot be reached without appropriate gate insulators that are scalable to the nanometre range. Typically used oxides such as SiO 2 , Al 2 O 3 and HfO 2 are, however, amorphous when scaled, and 2D hexagonal boron nitride exhibits excessive gate leakage currents. Here, we show that epitaxial calcium fluoride (CaF 2 ), which can form a quasi van der Waals interface with 2D semiconductors, can serve as an ultrathin gate insulator for 2D devices. We fabricate scalable bilayer MoS 2 field-effect transistors with a crystalline CaF 2 insulator of ~2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. Our devices exhibit low leakage currents and competitive device performance characteristics, including subthreshold swings down to 90 mV dec −1 , on/off current ratios up to 10 7 and a small hysteresis. High-performance MoS 2 transistors can be created using 2-nm-thick CaF 2 as a gate insulator, which forms a quasi van der Waals interface with the 2D semiconductor.

The paper presents the methods of assessing the technical condition of varistor surge arresters used in laboratory tests and in operation—performed without disconnecting the arresters from the network. The analysis of the diagnostic methods was supplemented with the results of the measurements of the leakage current of arresters coming directly from their production and used in the power industry. Among the available methods of evaluating the technical condition of arresters, mainly indicator solutions (temperature and operation counter) and the measurement of the selected parameters of the leakage current are used. In the latter, the method of determining the resistive component of the leakage current, determined on the basis of the analysis of the voltage and current waveforms, or only the arrester current, has become widespread. In this type of measurement, current clamps are used in the operation, and additionally, in voltage measurements, voltage transformers are used, where you have to take into account the fundamental, additional sources of errors discussed in the article. These errors and the dispersion resulting from the production technology may fundamentally hinder the proper assessment of the technical condition; hence, it is so important to properly recognize the listed basic sources of measurement uncertainty. In addition, the analysis should take into account three factors related to external conditions: temperature, the voltage applied to the arrester, and the content of higher harmonics in the supply voltage, for which appropriate methods have been provided to determine the active component of the leakage current for reference conditions. This article presents the results of the measurements of the leakage currents of surge arresters measured with various methods.

As an important power storage device, the demand for capacitors for high-temperature applications has gradually increased in recent years. However, drastically degraded energy storage performance due to the critical conduction loss severely restricted the utility of dielectric polymers at high temperatures. Hence, we propose a facile preparation method to suppress the conductivity loss of polyimide (PI) films by inserting boron nitride interlayer. The experimental results and computational simulations indicate that consecutive boron nitride interlayer has better effect on suppressing leakage current density of the entire material compared with uniform dispersed boron nitride nanosheet (BNNS) composite films. The experimental results show that the leakage current density of PI films is reduced by an order of magnitude and a classy energy density of 2.58 J/cm3 at a charge–discharge efficiency of 90% has been achieved at 150 °C, far better than pristine PI (0.75 J/cm3 of energy density and 65% of efficiency under 275 kV/mm and at 150 °C). The method we reported in this work is applicable to a variety of polymer dielectric films produced by solution casting for elevated temperature energy storage application.Graphical abstractAiming at the main problem of drastically degraded of energy storage performance caused by the sharp increase of leakage current of polymer dielectric film at high temperature, the energy storage performance of PI at 150 °C is improved by embedding boron nitride intermediate layer in PI.

Layered dielectric materials and their van der Waals (vdW) heterostructures offer high potential for next-generation two-dimensional (2D) electronic devices, but materials that combine a wide bandgap and high dielectric constant are rare. Here, we present the controllable synthesis of quasi-vdW layered samarium oxysulfate (Sm 2 O 2 SO 4 ) single crystals via a molten-salt-assisted chemical vapor deposition (CVD) method. These atomically thin crystals exhibit remarkable dielectric properties, including a wide bandgap (~5.54 eV), high dielectric constant (~18), robust breakdown voltage (>12 MV cm -1 ) and good thermal reliability. By integrating ultrathin Sm 2 O 2 SO 4 nanoplates with 2D molybdenum disulfide (MoS 2 ) via vdW forces, we fabricate field-effect transistors (FETs) showing a subthreshold swing down to 65.2 mV dec -1 , hysteresis down to 5.4 mV, on/off current ratios of ~10 9 , and gate leakage currents down to around 7 × 10 -7  A cm -2 . Furthermore, a high gate coupling ratio (GCR ~ 0.83) non-volatile memory device was developed based on the MoS 2 /h-BN/MLG/Sm 2 O 2 SO 4 /MLG heterostructure. The flash memory achieves ultrafast (~50 ns) programming/erasing operations, robust endurance (>2000 cycles) and long-term retention (>10 years). This work shows promising results for the integration of Sm 2 O 2 SO 4 as a high- κ dielectric in future 2D devices, with implications for low-power, high-performance electronics. van der Waals (vdW) dielectric materials with a wide bandgap and high dielectric constant are necessary for the development of 2D electronics. Here, the authors report the synthesis of quasi-vdW layered Sm 2 O 2 SO 4 thin crystals, showing a bandgap of ~5.54 eV and a dielectric constant ~18, leading to high performance 2D MoS 2 transistors.

Mitigating the oxidation susceptibility of Sn remains a critical issue for improving the environmental stability of lead-free perovskites. Herein, we show that the oxidized surface layer of Sn-based perovskites can be utilized to improve transistor performance, rather than being entirely suppressed. We report perovskite-IGZO junction field-effect transistors that use this oxidized layer to suppress gate current to below 10 −10  A, enabling enhancement-mode operation. We refer to these as barriered junction field-effect transistors. The combination of the gate leakage suppression and high polarizability of the perovskite layer results in a field-effect mobility of 29.4 cm 2 V −1 s −1 , subthreshold swing of 67.1 mV dec −1 , and on/off current ratio exceeding 10 5 under ≤1 V operation. These devices maintain stable operation in ambient conditions. Furthermore, we demonstrate their applicability by constructing logic gates such as NOT, NOR and NAND. These findings highlight the potential of exploiting Sn-based perovskite oxidation to advance electronic devices. Kim et al. report the oxidation of Sn-based perovskites, previously considered as detrimental, can be exploited to suppress the gate leakage current and enhance transistor performance and stability, enabling low-voltage logic operation using perovskite-IGZO junction field-effect transistors.