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The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

In this study, a novel Improved Affine Algorithm (IAA) for color image encryption is proposed. Affine Algorithm (AA) is generally known as an algorithm used for plain text encryption. In the proposed IAA algorithm, Linear Feedback Shift Register (LFSR), XOR encryption, and the AA are combined for color images encryption. The plane image is firstly split into three channels: R, G, and B. The RGB channel image is encrypted using AA encryption with ten keys based on pixel locations and pixel values. The rows and columns of the image are encrypted with LFSR keys and XOR encryption procedures. Finally, the proposed algorithm is tested in Matlab environment to obtain the Histogram, Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Unified Average Changing Intensity (UACI), Number of Pixel Change Rate (NPCR), and Entropy analyses. The values are compared with other algorithms. The results show that the proposed image encryption algorithm is secure and powerful, outperforming other algorithms.

Images are considered crucial for conveying information due to their visualisation properties and capacity to hold a large amount of data. To safeguard image data from potential risks of information leakage, numerous image encryption algorithms have been developed. These algorithms often make use of chaotic maps, known for their high unpredictability, ergodicity, and sensitivity to parameters and initial values. This paper introduces a new chaos-based digital image encryption algorithm to protect digital images from unauthorised access or attacks. The algorithm heavily relies on permutation and diffusion processes. Specifically, it employs two rounds of pixel permutation using a Tinkerbell chaotic map sequence on the source image and two rounds of pixel diffusion using the Linear Feedback Shift Register and Logistic Map sequences on the permuted image. The encryption algorithm’s effectiveness is thoroughly examined through various cryptanalysis techniques, including key space analysis, information entropy, correlation coefficient, differential attack, key sensitivity, histogram analysis, occlusion attack, noise attack, and encryption execution time. The experimental results are then compared with the most recent literature to demonstrate the algorithm’s reliability and its ability to withstand diverse attacks. Notably, the proposed algorithm stands out as a secure and viable encryption solution, requiring less computational time than previous studies, thus making it a more practical option for real-world applications.

A pseudo-random signal generator based on 0.5μm CMOS technology is presented, and it is applied for an auto-zero operational amplifier. The generator circuit includes a linear feedback shift register for generating pseudo-random sequences, and a multi-level counter module for counting the system clock pulses. A group of pseudo-random codes generated by the linear feedback shift register are as the initial value of the counter. When the counter reaches the maximum value, the output of the counter will control the output signal to flip. At the same time, a new group of the pseudo-random code will reset the counter again, and finally generate a square wave signal whose frequency varies randomly. The generator circuit is simulated and verified. The simulation results show that the frequency of the output signal can vary from 2 kHz to 4 kHz with random characteristic. The generated pseudo-random signal can be used for the switching clock control of the auto-zero operational amplifier offset calibration circuit, so that the switching glitch of the auto-zero op-amp is random, which can significantly reduce the harmonics in the output signal of the op-amp.

Conventionally, a linear feedback shift register (LFSR) constitutes linear sets of sequences with predictable periods, which are considered vulnerable to intruders. Besides, an LFSR limits the sequences of scan-for-test patterns. This work introduces a private key, which is a collection of keywords, to program the feedback coefficients and initial states of the LFSR, where each keyword modulates the LFSR with a different polynomial of the same degree. That is, each polynomial generates a linear set of sequences. Consequently, the aggregate polynomial has a set of unpredictable and nonlinear sequences with high statistical randomness. The keyword, which holds the coefficients and initial states of the LFSR, can be managed in a few bits and stored in first-in first-out memory array. HSPICE simulations for 90 nm CMOS technology verify the functionality and speed of the proposed programmable feedback shift register (PFSR) of size 16-bit with 64 keywords. Results show a clock speed of 500 MHz with a power consumption of 73 µW and transistor count of 37,593, wherein the overall period has 4,194,240 unpredictable nonlinear sequences that surpass most LFSR structures. The PFSR can be suited for ASIC and reconfigurable HDL synthesis for efficient stream cipher and scan-for-test applications.

In this paper, we discuss the properties of the derivative of a special function, and propose a general approach to estimating a class of trigonometric sums based on the derivative of the special function. Then we apply the approach to three trigonometric sums and get three new estimates. Using the estimate of the first trigonometric sum, we deduce new upper and lower bounds of the arithmetic mean value for a trigonometric sum of Vinogradov. Using the estimate of the second trigonometric sum, we derive a new upper bound on the imbalance properties of Linear Feedback Shift Register subsequences. We also deduce a new lower bound on the nonlinearity of the Carlet–Feng vectorial Boolean function with the estimate of the third trigonometric sum.

Data security is of the utmost importance in the domain of real-time environmental monitoring systems, particularly when employing advanced context-aware intelligent visual analytics. This paper addresses a significant deficiency in the Global System for Mobile Communications (GSM), a widely employed wireless communication system for environmental monitoring. The A5/1 encryption technique, which is extensively employed, ensures the security of user data by utilizing a 64-bit session key that is divided into three linear feedback shift registers (LFSRs). Despite the shown efficacy, the development of a probabilistic model for assessing the vulnerability of breaking or intercepting the session key (Kc) has not yet been achieved. In order to bridge this existing knowledge gap, this study proposes a probabilistic model that aims to evaluate the security of encrypted data within the framework of the Global System for Mobile Communications (GSM). The proposed model implements alterations to the current GSM encryption process by the augmentation of the quantity of Linear Feedback Shift Registers (LFSRs), consequently resulting in an improved level of security. The methodology entails increasing the number of registers while preserving the session key’s length, ensuring that the key length specified by GSM standards remains unaltered. This is especially important for environmental monitoring systems that depend on real-time data analysis and decision-making. In order to elucidate the notion, this analysis considers three distinct scenarios: encryption utilizing a set of five, seven, and nine registers. The majority function is employed to determine the registers that will undergo perturbation, hence increasing the complexity of the bit arrangement and enhancing the security against prospective attackers. This paper provides actual evidence using simulations to illustrate that an increase in the number of registers leads to a decrease in the vulnerability of data interception, hence boosting data security in GSM communication. Simulation results demonstrate that our method substantially reduces the risk of data interception, thereby improving the integrity of context-aware intelligent visual analytics in real-time environmental monitoring systems.

Many security-related scenarios including cryptography depend on the random generation of passwords, permutations, Latin squares, CAPTCHAs and other types of non-numerical entities. Random generation of each entity type is a different problem with different solutions. This study is an attempt at a unified solution for all of the mentioned problems. This paper is the first of its kind to pose, formulate, analyze and solve the problem of random object generation as the general problem of generating random non-numerical entities. We examine solving the problem via connecting it to the well-studied random number generation problem. To this end, we highlight the challenges and propose solutions for each of them. We explain our method using a case study; random Latin square generation.

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in designing the entire LFSR structure are design cost and energy efficiency, which are highly dependent on the SR structure. In the proposed study, the structural characteristics and problems of existing various types of SRs are presented, and new multi-layered serial-in-serial-out (SISO) and parallel-in-parallel-out (PIPO) SRs are proposed. In addition, we compare and analyze the area-time complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E. As a result, the proposed SISO and PIPO showed a performance improvement of more than 27% compared to the existing structure, which showed the best performance, and showed energy dissipation reduction rates of about 65% and 59%, respectively. In particular, we proposed multi-layer wiring that can reduce energy dissipation and verified through simulation that it can save up to 24.8%.

Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.