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"Memory (Computers)"
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Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing
Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge₂Sb₂Te₅). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb₂Te₃) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.
Journal Article
Superficial layers of the medial entorhinal cortex replay independently of the hippocampus
The hippocampus is thought to initiate systems-wide mnemonic processes through the reactivation of previously acquired spatial and episodic memory traces, which can recruit the entorhinal cortex as a first stage of memory redistribution to other brain areas. Hippocampal reactivation occurs during sharp wave–ripples, in which synchronous network firing encodes sequences of places. We investigated the coordination of this replay by recording assembly activity simultaneously in the CA1 region of the hippocampus and superficial layers of the medial entorhinal cortex. We found that entorhinal cell assemblies can replay trajectories independently of the hippocampus and sharp wave–ripples. This suggests that the hippocampus is not the sole initiator of spatial and episodic memory trace reactivation. Memory systems involved in these processes may include nonhierarchical, parallel components.
Journal Article
An Effective Selection of Memory Technologies for TCAM to Improve the Search Operations: Demonstration of Memory Efficiency in SDN Recovery
Ternary Content-Addressable Memory (TCAM) is used for storing the flow tables in software-defined networking (SDN)-based OpenFlow switches. However, the TCAM can store only a certain number of flow tables (8000). Moreover, when the switch flow tables need to be updated due to the link failure in the SDN, further updates may be lost due to the flow tables limit of the TCAM space. Hence, to resolve this issue, other memories need to be used in conjunction with TCAM to enhance the memory operations of TCAM. When considering which flash memory technology is to be used in conjunction with TCAM, we need to balance several factors to ensure optimal performance, speed, endurance, reliability, integration complexity, and cost-effectiveness. Hence, it leads to a multi-criteria decision-making problem regarding the selection of other memory technologies such as 3D XPoint, Magnetoresistive RAM, Resistive RAM, and Ferroelectric RAM. In this paper, we use the analytical network process (ANP) method to select the suitable technology in conjunction with TCAM, considering the features of the memory technologies for Software-Defined Internet-of-Things (SD-IoT). We provide a comprehensive numerical model leveraging the ANP to rank the memory technologies regarding their weights. The highest weights identify the most suitable technology for TCAM. We perform simulations to show the effectiveness of the mathematical model utilizing the ANP. The results show that the suggested methodology reduces the recovery delay, improves the packets received ratio (PRR), decreases the jitter, and increases the throughput.
Journal Article
Recent Research for HZO-Based Ferroelectric Memory towards In-Memory Computing Applications
The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or ‘logic-in-memory’ computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them.
Journal Article
Driving for More Moore on Computing Devices with Advanced Non-Volatile Memory Technology
As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing.
Journal Article
Magnetic ratchet for three-dimensional spintronic memory and logic
A layered on-chip structure of magnetic thin films is engineered to permit the vertical transfer of magnetic information over near-atomic distances.
A new dimension for magnetic logic
In conventional microelectronic chips, digital data are stored and manipulated in two dimensions in an
x
–
y
mesh of cells. Here Reinoud Lavrijsen and colleagues present an experimental demonstration of a new approach that exploits the rarely used third dimension to potentially enhance the performance of future spintronic devices. The system uses a layered structure of magnetic thin films engineered to permit the vertical transfer of magnetic information in an
x–y–z
lattice across near-atomic distances above a silicon surface.
One of the key challenges for future electronic memory and logic devices is finding viable ways of moving from today’s two-dimensional structures, which hold data in an
x
–
y
mesh of cells, to three-dimensional structures in which data are stored in an
x
–
y
–
z
lattice of cells. This could allow a many-fold increase in performance. A suggested solution is the shift register
1
,
2
—a digital building block that passes data from cell to cell along a chain. In conventional digital microelectronics, two-dimensional shift registers are routinely constructed from a number of connected transistors. However, for three-dimensional devices the added process complexity and space needed for such transistors would largely cancel out the benefits of moving into the third dimension. ‘Physical’ shift registers, in which an intrinsic physical phenomenon is used to move data near-atomic distances, without requiring conventional transistors, are therefore much preferred. Here we demonstrate a way of implementing a spintronic unidirectional vertical shift register between perpendicularly magnetized ferromagnets of subnanometre thickness, similar to the layers used in non-volatile magnetic random-access memory
3
. By carefully controlling the thickness of each magnetic layer and the exchange coupling between the layers, we form a ratchet that allows information in the form of a sharp magnetic kink soliton to be unidirectionally pumped (or ‘shifted’) from one magnetic layer to another. This simple and efficient shift-register concept suggests a route to the creation of three-dimensional microchips for memory and logic applications.
Journal Article
Toward a Universal Memory
When it comes to computers, MP3 players, digital cameras, and other electronic gadgets, there is no such thing as too much memory. Today's dominant solid-state memory technologies---static RAM, dynamic RAM, and Flash---have been around for a long time. Here, Akerman explores the different advantages and disadvantages of these three technologies.
Journal Article
A Facile Hydrothermal Synthesis and Resistive Switching Behavior of α-Fesub.2Osub.3 Nanowire Arrays
A facile hydrothermal process has been developed to synthesize the α-Fe[sub.2]O[sub.3] nanowire arrays with a preferential growth orientation along the [110] direction. The W/α-Fe[sub.2]O[sub.3]/FTO memory device with the nonvolatile resistive switching behavior has been achieved. The resistance ratio (R[sub.HRS]/R[sub.LRS]) of the W/α-Fe[sub.2]O[sub.3]/FTO memory device exceeds two orders of magnitude, which can be preserved for more than 10[sup.3]s without obvious decline. Furthermore, the carrier transport properties of the W/α-Fe[sub.2]O[sub.3]/FTO memory device are dominated by the Ohmic conduction mechanism in the low resistance state and trap-controlled space-charge-limited current conduction mechanism in the high resistance state, respectively. The partial formation and rupture of conducting nanofilaments modified by the intrinsic oxygen vacancies have been suggested to be responsible for the nonvolatile resistive switching behavior of the W/α-Fe[sub.2]O[sub.3]/FTO memory device. This work suggests that the as-prepared α-Fe[sub.2]O[sub.3] nanowire-based W/α-Fe[sub.2]O[sub.3]/FTO memory device may be a potential candidate for applications in the next-generation nonvolatile memory devices.
Journal Article
Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application
The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO2/SiOxNy/SiO2 (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability.
Journal Article