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A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field. This Perspective evaluates the state of the art in memristor-based electronics and explores the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing.

Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively. A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference.

HfO2 shows promise for emerging ferroelectric and resistive switching (RS) memory devices owing to its excellent electrical properties and compatibility with complementary metal oxide semiconductor technology based on mature fabrication processes such as atomic layer deposition. Oxygen vacancy (Vo), which is the most frequently observed intrinsic defect in HfO2-based films, determines the physical/electrical properties and device performance. Vo influences the polymorphism and the resulting ferroelectric properties of HfO2. Moreover, the switching speed and endurance of ferroelectric memories are strongly correlated to the Vo concentration and redistribution. They also strongly influence the device-to-device and cycle-to-cycle variability of integrated circuits based on ferroelectric memories. The concentration, migration, and agglomeration of Vo form the main mechanism behind the RS behavior observed in HfO2, suggesting that the device performance and reliability in terms of the operating voltage, switching speed, on/off ratio, analog conductance modulation, endurance, and retention are sensitive to Vo. Therefore, the mechanism of Vo formation and its effects on the chemical, physical, and electrical properties in ferroelectric and RS HfO2 should be understood. This study comprehensively reviews the literature on Vo in HfO2 from the formation and influencing mechanism to material properties and device performance. This review contributes to the synergetic advances of current knowledge and technology in emerging HfO2-based semiconductor devices.

Disentangling the attributes of a sensory signal is central to sensory perception and cognition and hence is a critical task for future artificial intelligence systems. Here we present a compute engine capable of efficiently factorizing high-dimensional holographic representations of combinations of such attributes, by exploiting the computation-in-superposition capability of brain-inspired hyperdimensional computing, and the intrinsic stochasticity associated with analogue in-memory computing based on nanoscale memristive devices. Such an iterative in-memory factorizer is shown to solve at least five orders of magnitude larger problems that cannot be solved otherwise, as well as substantially lowering the computational time and space complexity. We present a large-scale experimental demonstration of the factorizer by employing two in-memory compute chips based on phase-change memristive devices. The dominant matrix–vector multiplication operations take a constant time, irrespective of the size of the matrix, thus reducing the computational time complexity to merely the number of iterations. Moreover, we experimentally demonstrate the ability to reliably and efficiently factorize visual perceptual representations. Sensory signal attributes can be disentangled exploiting the computation-in-superposition capability of hyperdimensional computing, in-memory computing and associated intrinsic device-level stochasticity.

Compute-in-memory based on resistive random-access memory has emerged as a promising technology for accelerating neural networks on edge devices. It can reduce frequent data transfers and improve energy efficiency. However, the nonvolatile nature of resistive memory raises concerns that stored weights can be easily extracted during computation. To address this challenge, we propose RePACK, a threefold data protection scheme that safeguards neural network input, weight, and structural information. It utilizes a bipartite-sort coding scheme to store data with a fully on-chip physical unclonable function. Experimental results demonstrate the effectiveness of increasing enumeration complexity to 5.77 × 10 75 for a 128-column compute-in-memory core. We further implement and evaluate a RePACK computing system on a 40 nm resistive memory compute-in-memory chip. This work represents a step towards developing safe, robust, and efficient edge neural network accelerators. It potentially serves as the hardware infrastructure for edge devices in federated learning or other systems. Emerging compute-in-memory technologies show potential in edge AI; however, information protection tools need further development. Here, authors propose an on-chip scheme to simultaneously protect neural network input, weight, and structural information with low circuit overhead.

A key challenge for deep neural network algorithms is their vulnerability to adversarial attacks. Inherently non-deterministic compute substrates, such as those based on analog in-memory computing, have been speculated to provide significant adversarial robustness when performing deep neural network inference. In this paper, we experimentally validate this conjecture for the first time on an analog in-memory computing chip based on phase change memory devices. We demonstrate higher adversarial robustness against different types of adversarial attacks when implementing an image classification network. Additional robustness is also observed when performing hardware-in-the-loop attacks, for which the attacker is assumed to have full access to the hardware. A careful study of the various noise sources indicate that a combination of stochastic noise sources (both recurrent and non-recurrent) are responsible for the adversarial robustness and that their type and magnitude disproportionately effects this property. Finally, it is demonstrated, via simulations, that when a much larger transformer network is used to implement a natural language processing task, additional robustness is still observed. Adversarial attacks threaten deep neural networks. Here, authors show analog in-memory computing chips enhance robustness, attributed to stochastic noise properties. This is validated experimentally and in simulations with larger transformer models.

Motion detection is a primary visual function, crucial for the survival of animals in nature. Direction‐selective (DS) neurons can be found in multiple locations in the visual neural system, both in the retina and in the visual cortex. For instance, the DS ganglion cell in the retina provides a real‐time response to moving objects, which is much faster than the image recognition executed in the visual cortex. Such in‐retina biological signal processing capability is enabled by the spatiotemporal correlation within different receptive fields of the DS ganglion cells. Taking inspiration from the biological DS ganglion cells in the retina, the motion detection is demonstrated in an artificial neural network made of volatile resistive switching devices with short‐term memory effects. The motion detection arises from the spatiotemporal correlation between the adjacent excitatory and inhibitory receptive fields with short‐term memory synapses, closely resembling the physiological response of DS ganglion cells in the retina. The work supports real‐time neuromorphic processing of sensor data by exploiting the unique physics of innovative memory devices. Motion detection is a primary visual function and can be obtained in‐retina. It is enabled by the spatiotemporal correlation within different receptive fields of the direction‐selective ganglion cells. Taking inspiration from the mechanism of these ganglion cells, motion detection is demonstrated in an artificial neural network composed of volatile resistive switching devices with short‐term memory effects.

The composition: 10KNbO 3 -10Fe 2 O 3 -50B 2 O 3 -30V 2 O 5 (in mol%) is produced using the conventional melt quenching method and their corresponding glass–ceramic nanocomposites were studied. The structural properties of the as-quenched sample and its heat-treated samples were investigated using X-ray diffraction and differential thermal analysis. Density (ρ) was found to decrease with increasing average nanocrystallite size as the molar volume increases. Studies on thermoelectric power have been carried out. The glass–ceramic nanocomposite after 2 h of heating exhibits significant improvement of electrical conductivity. The activation energy (W), polaron radius (r p ) and other parameters have been estimated in the non-adiabatic region. The current–voltage (I–V) curve of each sample was measured. A temporal analysis of current & voltage in nonlinear I–V curves show pinched hysteresis loop, which is the memristor’s fingerprint. The glass–ceramic nanocomposite after 2 h of heating exhibits a large switching window. The results of the study enable us to predict that they will be helpful for future applications of non-volatile electronic-memory devices.

Resistive Random Access Memory (ReRAM) devices are being regarded as very promising choices for the future of non-volatile memory technology. The subject comprises crucial components like as material engineering, device architectural optimization, switching mechanisms, and improvements in reliability. This study examines the resistive switching capabilities of a device made from a ZrO 2 -CNT nanocomposite. The device was constructed utilizing a trilayer structure consisting of FTO/ZrO 2 -CNT/Ag, with the ZrO 2 -CNT film being fabricated by the spray coating technique. Incorporating 1wt% CNT into the ZrO 2 matrix reduces the bias voltage needed for resistive switching and approximately doubles the resistance ratio between HRS and LRS. The use of higher weight percentages of carbon nanotubes (CNT) negatively impacts the switching properties. The temperature dependence of resistance of ZrO 2 and ZrO 2 -1wt% CNT devices reveals that in ZrO 2 , O 2 vacancies align to create conducting filaments. On the other hand, in the ZrO 2 -CNT device, both vacancies of O 2 atoms and CNTs contribute to the production of conducting filaments. Inclusion of higher weight percentages of carbon nanotubes (CNT) leads to the formation of permanent conduction paths, which are electrical shorts and results in the loss of the switching capability.

Phase change materials present a unique type of materials that drastically change their electrical and optical properties on the introduction of an external electrical or optical stimulus. Although these materials have been around for some decades, they have only recently been implemented for on-chip photonic applications. Since their reinvigoration a few years ago, on-chip devices based on phase change materials have been making a lot of progress, impacting many diverse applications at a very fast pace. At present, they are found in many interesting applications including switches and modulation; however, phase change materials are deemed most essential for next-generation low-power memory devices and neuromorphic computational platforms. This review seeks to highlight the progress thus far made in on-chip devices derived from phase change materials including memory devices, neuromorphic computing, switches, and modulators.