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Memristor chaotic system has been attracted by many researchers because of the rich dynamical behaviors. However, some existed memristor chaotic systems have finite numbers of chaotic attractors. In this paper, a simple, effective method is given for designing the autonomous memristor chaotic systems of infinite chaotic attractors. Autonomous memristor chaotic systems are proposed from the start of memristor chaotic system counterparts. Three-dimensional, four-dimensional, and five-dimensional memristor chaotic systems are given in standard form with sine functions and tangent functions to prove the effectiveness of this method. Eventually, an analog circuit of three-dimensional memristor chaotic system is designed and implemented to prove its feasibility.

In this paper, a unified and open linear technology simulation program with integrated circuit emphasis (LTSPICE) memristor library is proposed. It is suitable for the analysis, design, and comparison of the basic memristors and memristor-based circuits. The library could be freely used and expanded with new LTSPICE memristor models. The main existing standard memristor models and several enhanced and modified models based on transition metal oxides such as titanium dioxide, hafnium dioxide, and tantalum oxide are included in the library. LTSPICE is one of the best software for analysis and design of electronic schemes. It is an easy to use, widespread, and free product with very good convergence. Memristors have been under intensive analysis in recent years due to their nano-dimensions, low power consumption, high switching speed, and good compatibility with traditional complementary metal oxide semiconductor (CMOS) technology. In this work, their behavior and potential applications in artificial neural networks, reconfigurable schemes, and memory crossbars are investigated using the considered memristor models in the proposed LTSPICE library. Furthermore, a detailed comparison of the presented LTSPICE memristor model library is conducted and related to specific criteria, such as switching speed, operating frequencies, nonlinear ionic drift representation, boundary effects, switching modes, and others.

ITO/WO[sub.x]/TaN and ITO/WO[sub.x]/AlO[sub.x]/TaN memory cells were fabricated as a neuromorphic device that is compatible with CMOS. They are suitable for the information age, which requires a large amount of data as next-generation memory. The device with a thin AlO[sub.x] layer deposited by atomic layer deposition (ALD) has different electrical characteristics from the device without an AlO[sub.x] layer. The low current is achieved by inserting an ultra-thin AlO[sub.x] layer between the switching layer and the bottom electrode due to the tunneling barrier effect. Moreover, the short-term memory characteristics in bilayer devices are enhanced. The WO[sub.x]/AlO[sub.x] device returns to the HRS without a separate reset process or energy consumption. The amount of gradual current reduction could be controlled by interval time. In addition, it is possible to maintain LRS for a longer time by forming it to implement long-term memory.

In this paper, we investigate the mathematical models of discrete memristors based on Caputo fractional difference and G–L fractional difference. Specifically, the integer-order discrete memristor is a special model of those two cases. The “∞”-type hysteresis loop curves are observed when input is the bipolar periodic signal. Meanwhile, numerical analysis results show that the area of hysteresis decreases with the increase of frequency of input signal and the decrease of derivative order. Moreover, the memory effect, characteristics and physical realization of the discrete memristors are discussed, and a discrete memristor with short memory effects is designed. Furthermore, discrete memristive systems are designed by introducing the fractional-order discrete memristor and integer-order discrete memristor to the Sine map. Chaos is found in the systems, and complexity of the systems is controlled by the parameter of the memristor. Finally, FPGA digital circuit implementation is carried out for the integer-order and fractional-order discrete memristor and discrete memristive systems, which shows the potential application value of the discrete memristor in the engineering application field.

Organic memristors are promising candidates for the flexible synaptic components of wearable intelligent systems. With heightened concerns for the environment, considerable effort has been made to develop organic transient memristors to realize eco‐friendly flexible neural networks. However, in the transient neural networks, achieving flexible memristors with biorealistic synaptic plasticity for energy efficient learning processes is still challenging. Herein, a biodegradable and flexible polymer‐based memristor, suitable for the spike‐dependent learning process, is demonstrated. An electrochemical metallization phenomenon for the conductive nanofilament growth in a polymer medium of poly (vinyl alcohol) (PVA) is analyzed and a PVA‐based transient and flexible artificial synapse is developed. The developed device exhibits superior biodegradability and stable mechanical flexibility due to the high water solubility and excellent tensile strength of the PVA film, respectively. In addition, the developed flexible memristor is operated as a reliable synaptic device with optimized synaptic plasticity, which is ideal for artificial neural networks with the spike‐dependent operations. The developed device is found to be effectively served as a reliable synaptic component with high energy efficiency in practical neural networks. This novel strategy for developing transient and flexible artificial synapses can be a fundamental platform for realizing eco‐friendly wearable intelligent systems. An interactive preprint version of the article can be found here: https://doi.org/10.22541/au.166603245.58711630/v1. A biodegradable and flexible polymer‐based memristor for eco‐friendly artificial synapses is demonstrated. The developed device exhibits superior biodegradability and mechanical flexibility due to the high water solubility and excellent tensile strength of the polymer, respectively. Moreover, the memristors are operated as reliable synaptic cells with optimized synaptic plasticity, which is ideal for artificial neural networks with high energy efficiency.

The continuous memristor is a popular topic of research in recent years, however, there is rare discussion about the discrete memristor model, especially the locally active discrete memristor model. This paper proposes a locally active discrete memristor model for the first time and proves the three fingerprints characteristics of this model according to the definition of generalized memristor. A novel hyperchaotic map is constructed by coupling the discrete memristor with a two-dimensional generalized square map. The dynamical behaviors are analyzed with attractor phase diagram, bifurcation diagram, Lyapunov exponent spectrum, and dynamic behavior distribution diagram. Numerical simulation analysis shows that there is significant improvement in the hyperchaotic area, the quasi periodic area and the chaotic complexity of the two-dimensional map when applying the locally active discrete memristor. In addition, antimonotonicity and transient chaos behaviors of system are reported. In particular, the coexisting attractors can be observed in this discrete memristive system, resulting from the different initial values of the memristor. Results of theoretical analysis are well verified with hardware experimental measurements. This paper lays a great foundation for future analysis and engineering application of the discrete memristor and relevant the study of other hyperchaotic maps.

Information in conventional digital computing platforms is encoded in the steady states of transistors and processed in a quasi-static way. Memristors are a class of emerging devices that naturally embody dynamics through their internal electrophyiscal processes, enabling nonconventional computing paradigms with enhanced capability and energy efficiency, such as reservoir computing. Here, we report on a dynamic memristor based on LiNbO 3 . The device has nonlinear I-V characteristics and exhibits short-term memory, suitable for application in reservoir computing. By time multiplexing, a single device can serve as a reservoir with rich dynamics which used to require a large number of interconnected nodes. The collective states of five memristors after the application of trains of pulses to the respective memristors are unique for each combination of pulse patterns, which is suitable for sequence data classification, as demonstrated in a 5 × 4 digit image recognition task. This work broadens the spectrum of memristive materials for neuromorphic computing.

Artificial synapses and neurons are crucial milestones for neuromorphic computing hardware, and memristors with resistive and threshold switching characteristics are regarded as the most promising candidates for the construction of hardware neural networks. However, most of the memristors can only operate in one mode, that is, resistive switching or threshold switching, and distinct memristors are required to construct fully memristive neuromorphic computing hardware, making it more complex for the fabrication and integration of the hardware. Herein, we propose a flexible dual‐mode memristor array based on core–shell CsPbBr3@graphdiyne nanocrystals, which features a 100% transition yield, small cycle‐to‐cycle and device‐to‐device variability, excellent flexibility, and environmental stability. Based on this dual‐mode memristor, homo‐material‐based fully memristive neuromorphic computing hardware—a power‐free artificial nociceptive signal processing system and a spiking neural network—are constructed for the first time. Our dual‐mode memristors greatly simplify the fabrication and integration of fully memristive neuromorphic systems. An optically modulated dual‐mode memristor array based on core–shell CsPbBr3@graphdiyne nanocrystals is developed, which can emulate both the artificial synapses and neurons. Based on this dual‐mode memristor, homo‐material‐based fully memristive neuromorphic computing hardware including a power‐free artificial nociceptive signal processing system and a spiking neural network are constructed for the first time.

Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips.

Neural networks based on memristive devices 1 – 3 have the ability to improve throughput and energy efficiency for machine learning 4 , 5 and artificial intelligence 6 , especially in edge applications 7 – 21 . Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks 22 – 28 . This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even ‘mortal computing’ 25 , 29 , 30 . Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications. Chips with 256 × 256 memristor arrays that were monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry achieved 2,048 conductance levels in individual memristors.