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Solid-state refrigeration offers potential advantages over traditional cooling systems, but few devices offer high specific cooling power with a high coefficient of performance (COP) and the ability to be applied directly to surfaces. We developed a cooling device with a high intrinsic thermodynamic efficiency using a flexible electrocaloric (EC) polymer film and an electrostatic actuation mechanism. Reversible electrostatic forces reduce parasitic power consumption and allow efficient heat transfer through good thermal contacts with the heat source or heat sink. The EC device produced a specific cooling power of 2.8 watts per gram and a COP of 13. The new cooling device is more efficient and compact than existing surface-conformable solid-state cooling technologies, opening a path to using the technology for a variety of practical applications.

Anode-free lithium batteries represent a promising avenue for high-energy-density storage, yet their practical application is hindered by lithium inventory loss from parasitic interfacial reactions, cathode degradation, and limited Li + reversibility. Herein, we propose a polyolefin separator integrated with a Li 2 S@C sacrificial layer, achieving multiscale interfacial stabilization in Ah-class anode-free pouch cells. This approach simultaneously replenishes the customized Li + inventory during the formation cycle and establishes the lithium polysulfide-containing cathode interface with high-voltage tolerance (till 4.5 V). Real-time tracking via in-situ electrochemical impedance spectroscopy and transmission-mode operando X-ray diffraction reveals accelerated Li + diffusion kinetics and stabilized phase evolution in LiNi 0.8 Co 0.1 Mn 0.1 O 2 cathode interfaced with Li 2 S@C|PE prelithiation separator. Consequently, a 1.22 Ah pouch cell with an Ag-modified Cu foil and LiNi 0.8 Co 0.1 Mn 0.1 O 2 cathode is assembled with Li 2 S@C|PE separator and exhibits gravimetric and volumetric energy densities of 450 Wh kg -1 and 1355 Wh L -1 , respectively. This prelithiation protocol demonstrates upscaling potential and generic applicability to secure the interfacial chemistries for anode free/less lithium metal batteries. Anode-free lithium batteries are hindered by lithium inventory loss from parasitic interfacial reactions, cathode degradation, and limited Li + reversibility. Here, authors propose a prelithiation separator engineering to enable multiscale interfacial stabilization in Ah-class anode-free pouch cells.

Force and strain sensors made of soft materials enable robots to interact intelligently with their surroundings. Capacitive sensing is widely adopted thanks to its low power consumption, fast response, and facile fabrication. Capacitive sensors are, however, susceptible to electromagnetic interference and proximity effects and thus require electrical shielding. Shielding has not been previously implemented in soft capacitive sensors due to the parasitic capacitance between the shield and sensing electrodes, which changes when the sensor is deformed. We address this crucial challenge by patterning the central sensing elastomer layer to control its compressibility. One design uses an ultrasoft silicone foam, and the other includes microchannels filled with liquid metal and air. The force resolution is sub-mN both in normal and shear directions, yet the sensor withstands large forces (>20 N), demonstrating a wide dynamic range. Performance is unaffected by nearby high DC and AC electric fields and even electric sparks. Capacitive soft force sensors require electrical shielding from electromagnetic interference, but this shielding can mess with the effectiveness of the sensing electrodes. Here, Aksoy et al. solve this problem by patterning the central sensing elastomer layer to control its compressibility.

Dielectric capacitors are vital for modern power and electronic systems, and accurate assessment of their dielectric properties is paramount. However, in many prevailing reports, the fringing effect near electrodes and parasitic capacitance in the test circuit were often neglected, leading to overrated dielectric performances. Here, the serious impacts of the fringing effect and parasitic capacitance are investigated both experimentally and theoretically on different dielectrics including Al 2 O 3 , SrTiO 3 , etc. The deviations are more critical for the measurements of capacitors using asymmetric electrodes with different areas and for dielectrics with a lower dielectric constant, and differences tested in silicone oil and air environments should be noticed. A method to calibrate the parasitic capacitance of the test circuit is also raised for ensuring the accuracy of measured dielectric performances. Enlarging the electrode diameter and/or thinning the sample can reduce the above deviations, and thus a general standard of setting capacitor configurations is proposed for the measurement validity. Our study clearly demonstrates that it is necessary to mitigate the fringing effect and subtract the parasitic capacitance to solve the problem on overrated dielectric performances, which is very important for the development of the dielectric research in a healthy and orderly way. The authors find that the dielectric performance of capacitors will be significantly overestimated due to the influences of fringing effect and parasitic capacitance. Methods to solve the problem are proposed to ensure measurement validity.

With the increase in demand for renewable energy, photovoltaic power generation is gradually becoming the most promising new energy source. However, the electrical connection of PV cells to the grid, and parasitic capacitance between the PV cell and the ground can introduce severe leakage currents into the grid. The scientific community has developed various topology-based techniques to suppress leakage currents. This paper is dedicated to a review of these techniques. Firstly the H5, HERIC, FB-DCBP, oH5, H8, and H6 are analyzed. These techniques are then reviewed more fully in terms of quality, efficiency, size, and complexity. All six of these topologies can meet the requirements for leakage current suppression, and there is an increasing trend toward reducing the size and simplifying topologies. Finally, future trends in topology-based techniques for suppressing leakage currents are predicted. The significance of this paper is that it provides a comprehensive review and summary of the various topology-based techniques for suppressing leakage currents.

The Shunt-LDO regulator has been integrated in the ATLAS and the CMS pixel detector RD53 front-end chip to implement the serial powering scheme which both experiments have chosen as the baseline option for the HL-LHC upgrade. The performance of the integrated regulators has been characterized and specific design challenges have been identified which are related to layout parasitics and shallow trench isolation (STI) stress effects. In addition the functionality of circuits which address crucial system level aspects like the protection against overvoltage/overload has been verified.

α particles must be monitored to be managed as radioactive diagnostic agents or nuclear activity indicators. The new generation of perovskite detectors suffer from limited energy resolution, which affects spectroscopy and imaging applications. Here, we report that the solution-grown CsPbBr 3 crystal exhibits a low and stable dark current (34.6 nA·cm −2 at 200 V) by thinning the as-grown crystal to decrease the high concentration CsPb 2 Br 5 phase near the surface. The introduction of the Schottky electrode for the CsPbBr 3 detector further reduces the dark current and improves the high-temperature stability. An energy resolution of 6.9% is achieved with the commercial electronic system, while the effects of air scattering and absorption are investigated. Moreover, 1.1% energy resolution is recognized by a full-customized readout application-specific integrated circuit without any additional signal processing, which matches well with the given parameters of the CsPbBr 3 detector by reducing the parasitic capacitance and electronic noise. By developing a synergistic strategy of thinning the perovskite crystal, employing Schottky electrode and full-customised readout application specific integrated circuit to supress dark current and electronic noise, the authors report an energy resolution of 1.1% for perovskite α-particle detector.

This letter presents a low‐distortion bootstrapped switch for improving sampling network linearity. The dynamically driven gate approach and the dynamically driven deep N‐well technique are proposed to reduce the parasitic capacitance at crucial nodes. Simulated in a 180 nm CMOS process, the proposed switch achieves a total harmonic distortion (THD) of −101.3 dB at an 80 MHz sampling frequency. This is a 20.7 dB increase in THD over the conventional switch. This letter presents a low‐distortion bootstrapped switch for improving sampling network linearity. The dynamically driven gate approach and the dynamically driven deep N‐well technique are proposed to reduce the parasitic capacitance at crucial nodes.

In this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of RRAM states and fast reading speed in the nanosecond range. The sense margin of the proposed circuit has improved as the array size increases, enhancing its application for advanced node RRAM array manufacture. Compared with conventional circuits, the proposed circuit achieved power consumption reduction of 6% and area reduction of 46.9 um 2 , resulting in a 97.5% reduction in area, providing an effective solution to address the cost and chip size challenges associated with RRAM industrialization.

Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS 2 nFETs and WSe 2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (−16%), reduced time to write (−72%) and lowered dynamic power (−60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications. Simulations show that two-dimensional-material-based static random-access memory (SRAM) circuits leverage their low parasitic capacitance, counteracting performance declines due to increased interconnect resistance and potentially surpassing Si-based SRAM in terms of both performance and energy efficiency at advanced technology nodes.