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This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

Electroluminescence and electron avalanching are the physical effects used in two-phase argon and xenon detectors for dark matter searches and neutrino detection, to amplify the primary ionization signal directly in cryogenic noble-gas media. We review the concepts of such light and charge signal amplification, including a combination thereof, both in the gas and in the liquid phase. Puzzling aspects of the physics of electroluminescence and electron avalanching in two-phase detectors are explained, and detection techniques based on these effects are described.

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

Microwave sources based on ultrastable lasers and optical frequency combs (OFCs) exhibit ultralow phase noise and ultrahigh-frequency stability, which are important for many applications. Herein, we present a microwave source that is phase-locked to an ultrastable continuous-wave laser, with a relative frequency instability of 7 × 10−16 at 1 s. An Er:fiber-based OFC and an optic-to-electronic converter with low residual noise are employed to confer optical frequency stability on the 9.6 GHz microwave signal. Instead of using the normal cascaded Mach–Zehnder interferometer method, we developed a microwave regeneration method for converting optical pulses into microwave signals to further suppress the additional noise in the optic-to-electronic conversion process. The microwave regeneration method employs an optical-to-microwave phase detector based on a fiber-based Sagnac loop to produce the error signal between a 9.6 GHz dielectric resonator oscillator (DRO) and the OFC. The 9.6 GHz microwave (48th harmonic of the comb’s repetition rate) signal with the frequency stability of the ultrastable laser was achieved using a DRO that was phase-locked to the optical comb. Preliminary evaluations showed that the frequency instability of the frequency synthesizer from the optical to the 9.6 GHz microwave signal was approximately 2 × 10−15 at 1 s, the phase noise was −106 dBc Hz−1 at 1 Hz, and the timing noise was approximately 9 as Hz−1/2 (phase noise approx. −125 dBc Hz−1). The 9.6 GHz signal from the photonic microwave source exhibited a short-term relative frequency instability of 2.1 × 10−15 at 1 s, which is 1.5 times better than the previous results.

A new phase detector for high-speed applications is proposed in this paper. Due to their long reset path, conventional phase detectors can work in lower frequencies. However, the proposed phase detector has lower reset path delay in which makes it suitable for high-speed phase locked loops (PLL) and delay locked loops (DLL). Moreover, this new phase detector uses a few transistors. The proposed circuit is designed based on TSMC 0.13  μ m CMOS Technology. Simulations show lower reset path delay, blind zone and power consumption for proposed architecture in comparison with pervious related works. In addition, the circuit is able to detect phase offsets in about 80 ps and to work properly in frequencies near 3 GHz. Its blind zone is about 120 ps, while its reset path delay is about 80 ps. Furthermore, the power consumption of the proposed circuit at 128 MHz is found to be about 134 μ W .

A Mueller-Muller Phase Detector (MM PD) technology based on duo-binary four-level pulse amplitude modulation (DB PAM-4) with low complexity and high phase-detection density is presented. The proposed low complexity includes low phase-detection complexity and low space complexity of data processing. The waveform sifting technology simplifies 175 specific waveform changes into five fuzzy waveform change trends, reducing the complexity of subsequent phase detection. By making the data sample before the waveform sifting, the data bit width is reduced from 8 bit to 3 bit, which realizes data dimensionality reduction, greatly reduces the scale of subsequent auxiliary data, reduces the number of basic devices by 13.7%, and reduces the spatial complexity of data processing. The coherent coding of DB PAM-4 combined with waveform sifting increases the phase-detection density from 50% to 65% and improves both phase-detection density and phase-detection gain by 30%, and improves the jitter tolerance. Through the simulation of the clock and data recovery (CDR) model built by Cadence, the fast locking capability of CDR is verified.

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area.

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.

The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as a demodulation algorithm. However, resolver signals often come with quadrature errors and harmonics, which lead to a severe reduction in PLL accuracy. The conventional PLL does not consider the impact of the quadrature error, and the bandwidth of the PLL is much larger than the fundamental frequency of resolver signals for pursuing a low dynamic error. These reasons render the retention of resolver harmonics in the demodulation results. In this paper, a disturbance-compensated PLL (DC-PLL) is proposed, which consists of a phase detector for suppressing quadrature error and harmonics (SQEH-PD) and a second-order observer. Firstly, since the quadrature error does not change with the angle velocity, the pre-estimated quadrature error is used in the SQEH-PD to compensate for the quadrature error in resolver signals. Secondly, although the frequency of the harmonics changes with the velocity, the amplitudes of the harmonics do not change. Therefore, the pre-estimated amplitudes of harmonics and estimated angular position are used in the SQEH-PD to compensate for the harmonics in resolver signals. Thirdly, a second-order observer is designed to estimate the angular position and velocity by regulating the phase detector error. Compared with the conventional PLL, the proposed DC-PLL has a stronger anti-disturbance ability against the quadrature error and harmonics by configurating the phase detector error and the estimated position error, which have a linear relation. Simulation and experimental results prove the effectiveness of the proposed method.